In one or more aspects, the present invention improves the efficiency of soft information transfer within a soft-value processing apparatus, by reducing in some sense the “amount” of soft information transferred between constituent processor circuits within the apparatus, without forfeiting or otherwise compromising the transfer of “valuable” soft information. In one example, the soft values produced by a constituent processor circuit are identified as being reliable or unreliable according to a reliability threshold. Some or all of the unreliable values are omitted from a soft value information transfer to another constituent processor circuit, or they are quantized for such transfer. The reduction in memory requirements for soft information transfer advantageously allows the use of lower power, less complex, and less expensive circuitry than would otherwise be required in the apparatus, which may be, as a non-limiting example, a Turbo receiver in a wireless communication device.
Drawings
Claims24
A method of transferring soft information between constituent processor circuits in a soft-value processing apparatus, the method comprising:
generating a soft information set comprising a plurality of soft values at a first constituent processor circuit that acts as a soft information source for a second constituent processor circuit;
detecting low-reliability soft values among the plurality of soft values in the soft information set according to a defined reliability threshold;
obtaining a compressed soft information set by compressing the soft information set at least with respect to the low-reliability soft values;
and
transferring the compressed soft information set from the first constituent processor circuit to the second constituent processor circuit.
2 more elements
A soft-value processing apparatus comprising first and second constituent processor circuits, wherein the first constituent processor circuit comprises:
a soft information set generation circuit configured to generate a soft information set comprising a plurality of soft values indicating the reliability of data detections performed with respect to a set of input data values;
and
a soft value transfer circuit configured to:
detect low-reliability soft values among the plurality of soft values in the soft information set according to a defined reliability threshold;
obtain a compressed soft information set by compressing the soft information set at least with respect to the low-reliability soft values;
and
transfer the compressed soft information set from the first constituent processor circuit to the second constituent processor circuit, for use as extrinsic information by the second constituent processor circuit.
4 more elements
A wireless communication device comprising a soft-value processing apparatus, the soft-value processing apparatus comprising first and second constituent processor circuits, wherein the first constituent processor circuit comprises:
a soft information set generation circuit configured to generate a soft information set comprising a plurality of soft values indicating the reliability of data detections performed with respect to a set of input data values;
and
a soft value transfer circuit configured to:
detect low-reliability soft values among the plurality of soft values in the soft information set according to a defined reliability threshold;
obtain a compressed soft information set by compressing the soft information set at least with respect to the low-reliability soft values;
and
transfer the compressed soft information set from the first constituent processor circuit to the second constituent processor circuit, for use as extrinsic information by the second constituent processor circuit.
13 Dec 2032Estimated · howhide20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 322 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.
Purpose and implementation aspects: representation or format of variables, register sizes or word-lengths and quantization
Life of this patent
About 6 years 2 months of term left · ends 13 Dec 2032 (estimated)
Priority26 Jan 2012
Granted29 Apr 2014
Today12 Oct 2026
Term ends13 Dec 2032
Priority26 Jan 2012
Granted29 Apr 2014
Term ends13 Dec 2032
Application filedUS 13/358,978
Assigned to Telefonaktiebolaget Lm Ericsson (Publ)assignment of assignor's interest
PublishedUS 2013/0198591 A1
GrantedUS 8,713,414 B2
TodayWithin its term
Term endsEstimated, includes 322 days of adjustment
Description9,892 words
Summary1,422 words
#The present invention generally relates to soft information processing and particularly relates to the transfer of soft information within a soft-value processing apparatus.
#Soft information finds use in a variety of “belief propagation” systems, such as in communications signal decoding where, as a simple example, a series of soft decisions indicate whether corresponding bits in a received communication signal are more likely 1s or 0s. “Turbo” type receivers are a particularly well-known and useful example of soft information processing. Numerous technical references are available regarding the fundamental aspects of Turbo coding and decoding. See, for example, C. Berrou, A. Glavieux, et al., “Near Shannon limit error-correcting coding and decoding: Turbo-codes”, Proceedings of ICC 1993, Geneva, Switzerland, pp. 1064-1070; and C. Douillard, A. Picart, P. Didier, M. Jézéquel, C. Berrou, and A. Glavieux, “Iterative correction of intersymbol interference: turbo-equalization”, European Transactions on Telecommunications, Vol. 6, No. 5, September-October 1995, pp. 507-512.
#During the last two decades, the Turbo principle has been used in constructing a myriad of channel coding schemes, as well as iterative receiver approaches for applications beyond channel coding. However, in a basic Turbo decoding approach, the target receiver implements an iterative decoding structure in which two relatively simple constituent decoders exchange soft information, so that the probability estimates (“beliefs”) from one decoder aid the other decoder in refining its estimates. The iterative exchange of probability values—such as Log Likelihood Ratios or LLRs—allows Turbo-based coding and decoding schemes to achieve near Shannon limit performance, despite the use of relatively simple constituent codes.
Brief description of the drawings9 figures
#FIG. 1 is a block diagram of one embodiment of a soft-value processing apparatus.
#FIG. 2 is a block diagram of example compression processes applied to high-reliability and low-reliability soft values in a soft information set, for compression of that soft information set.
#FIG. 3 is a block diagram of one embodiment of parallel soft-value processes implemented in a soft-value processing apparatus.
Detailed description8,249 words
#FIG. 1 illustrates a soft-value processing apparatus 10 that includes first and second constituent processor circuits 12-1 and 12-2. The first constituent processor circuit 12-1 includes a soft information set generation circuit 14 configured to generate a soft information set 16 comprising a plurality of soft values 18. The soft values 18 indicate the reliability of data detections performed with respect to a set of input data values 20. As a non-limiting example, the input data values 20 are digital samples representing symbols or bits conveyed in a received communication signal.
#In an example case, the soft values 18 are, for example, Log Likelihood Ratios (“LLRs”) representing a ratio of the probability that a corresponding received signal bit value is a “1” to the probability that it is a “0.” Further, as will be shown, the constituent processor circuits 12 implement one or more Turbo-based processes, such as a demodulator performing bit/symbol detection in a demodulation process, where the demodulator process provides soft values to a decoder process in a feedfoward path and/or where the decoder process provides soft values to the demodulator in a feedback path. Thus, the constituent processors 12-1 and 12-2 are, as non-limiting examples, a demodulation circuit and an associated decoding circuit, or are cooperative pair of decoder circuits.
#Turning back to the diagram, the first constituent processor circuit 12-1 further includes a soft value transfer circuit 22—abbreviated as “SV transfer circuit 22” in the diagram—that is configured to detect low-reliability soft values 24 among the plurality of soft values 18 in the soft information set 16 according to a defined reliability threshold 28. Such detection may be performed after generation of the soft information set 16, or on the fly as soft values 18 are being computed.