Generation of interpolated samples for decision based decoding
AssigneeSK hynix memory solutions inc.
InventorsJason Bellorado, Marcus Marrow
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AssigneeSK hynix memory solutions inc.
InventorsJason Bellorado, Marcus Marrow
Estimating the term…
A plurality of interpolated samples is generated. Using a plurality of soft-decision detectors, error correction decoding is performed on the plurality of interpolated samples in order to obtain a plurality of decisions. From the plurality of decisions, one is selected by determining which of the plurality of soft-decision detectors are able to come to a decision during error correction decoding. It is determined whether a majority of the detectors that are able to come to a decision come to a same decision. If not, a decision associated with a greatest reliability is selected from the decision detectors that are able to come to a decision.
A system, comprising:
A method, comprising:
A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
Dependencies are inferred from the claim text.
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Joint error correction and other techniques: error control coding in combination with techniques for partial response channels, e.g. recording
Synchronisation based on error coding or decoding: phase recovery
Joint error correction and other techniques: error control coding in combination with channel estimation
Coding
About 5 years 2 months of term left · ends 16 Dec 2031 (estimated)
In storage and communication systems, a read signal (e.g., read back from storage media) or a received signal (e.g., received via a communications channel) is transformed from an analog signal to a digital signal. In order for downstream digital processors in a receiver or a read processor to operate properly, the timing parameters (e.g., frequency and phase) of an analog to digital converter must match that of desired timing parameters. For example, if a random sampling phase is used, at some phases the signal folds back constructively (i.e., increases signal power) whereas at other phases the signal folds back destructively (i.e., decreases signal power) and performance is degraded in the latter case.
Some systems use a closed loop system where there is a feedback path which adjusts the timing parameters of the analog to digital converter. This is often done using a known data portion of a sector or packet, for example a preamble portion and/or synchronization mark portion where the content is known ahead of time. It would be desirable if new techniques could be developed, for example that use simpler processing (which corresponds to a smaller die size and less cost) and/or improve the performance or efficiency of the system.
Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings.
FIG. 1 is a system diagram showing an embodiment of a read processor configured to perform interpolation based processing and a corresponding write processor.
FIG. 2 is a diagram showing an embodiment of interpolation performed by a 1 to 4 interpolator.
The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions.
A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.
FIG. 1 is a system diagram showing an embodiment of a read processor configured to perform interpolation based processing and a corresponding write processor. In the example shown, the read processor and write processor are used to read data from and write data to storage media (e.g., Flash storage or magnetic disk storage). In some other embodiments, the techniques described herein are used in a communications system and are implemented in a wired or wireless transmitter and/or receiver.