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US 8,713,411 B2Granted
Encoding and/or decoding memory devices and methods thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJun Jin Kong, Yong June Kim, Jae Hong Kim
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AssigneeSamsung Electronics Co., Ltd.
InventorsJun Jin Kong, Yong June Kim, Jae Hong Kim
Estimating the term…
Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.
A memory device, comprising:
A memory device, comprising:
A coding method, comprising:
A coding method, comprising:
Dependencies are inferred from the claim text.
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Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability…:…
In individual solid state devices: in multilevel memories
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words:…
Coding
About 4 years 5 months of term left · ends 2 Apr 2031 (estimated)
This application claims the benefit of Korean Patent Application No. 10-2008-0024929, filed on Mar. 18, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
1. Field
Example embodiments relate to error-control codes (ECC), for example, to ECC encoding/decoding methods for memory devices.
The above and/or other aspects, features, and advantages of example embodiments will become apparent and more readily appreciated from the following description of example embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a diagram illustrating a memory device according to example embodiments;
FIG. 2 is a diagram illustrating decoding operations of the decoder of FIG. 1, according to example embodiments;
Example embodiments will now be described more fully with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of example embodiments. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.