US 8,713,410 B2 · Data storage apparatus, memory control apparatus and method for controlling flash memories

Abstract

According to one embodiment, a data storage apparatus includes a channel controller, an error correction controller, and an additional correction module. The channel controller is configured to control writing to and reading from the nonvolatile memories of respective channels. The error correction controller is configured to use inter-channel error correction codes during any read process, performing inter-channel correction process on those of the data items read under the control of the channel controller, which have been designated. The additional correction module is configured to designate, in accordance with errors detected by the channel controller, data items to additionally correct, and to notify the data items so designated to the error correction controller while the channel controller is reading the data necessary in the inter-channel correction process.

Drawings

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Drawings

Claims11

Dependent claims

A data storage apparatus comprising:

a channel controller configured to control writing to and reading from each of nonvolatile memories of a plurality of channels, detect errors in data read from the nonvolatile memory of each channel and correct the errors;
an error correction controller configured to perform an inter-channel error correction process on first data designated by the channel controller, the designated data indicating that the errors cannot be corrected by the channel controller, wherein the inter-channel error correction process uses inter-channel error correction codes and the inter-channel error correction codes are generated by using the data of the channels written in the writing by the channel controller;
and
an additional correction module configured to designate second data to be subjected to an additional correction process and notify the error correction controller of the second data, if errors are detected in the second data by the channel controller while the channel controller is performing a corrective read process of reading data necessary to perform the inter-channel error correction process.

1 more element

A memory control apparatus for use in a data storage apparatus having nonvolatile memories of a plurality of channels, the control apparatus comprising:

a channel controller configured to control writing to and reading from the nonvolatile memories of the channels, detect errors in data read from the nonvolatile memory of each channel and correct the errors;
an error correction controller configured to perform an inter-channel error correction process on first data designated by the channel controller, the designated data indicating that the errors cannot be corrected by the channel controller, wherein the inter-channel error correction process uses inter-channel error correction codes and the inter-channel error correction codes are generated by using the data of the channels written in the writing by the channel controller;
and
an additional correction module configured to designate second data to be subjected to an additional correction process and notify the error correction controller of the second data, if errors are detected in the second data by the channel controller while the channel controller is performing a corrective read process of reading data necessary to perform the inter-channel error correction process.

1 more element

Dependencies are inferred from the claim text.

Description4,473 words

Summary297 words

#This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2011-014178, filed Jan. 26, 2011, the entire contents of which are incorporated herein by reference.

#Embodiments described herein relate generally to a data storage apparatus, a memory control apparatus and a method for controlling flash memories.

#In recent years, solid-state drives (SSDs) have been developed as data storage apparatuses, each using NAND flash memories (hereinafter referred to as “flash memories” in certain cases) that are rewritable nonvolatile memories.

Brief description of the drawings13 figures

#A general architecture that implements the various features of the embodiments will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate the embodiments and not to limit the scope of the invention.

#FIG. 1 is a block diagram explaining the configuration of a data storage apparatus according to an embodiment;

#FIG. 2 is a block diagram explaining the configuration of a flash memory controller according to the embodiment;

Detailed description3,916 words

#Various embodiments will be described hereinafter with reference to the accompanying drawings.

#In general, according to one embodiment, a data storage apparatus includes a channel controller, an error correction controller, and an additional correction module. The channel controller is configured to control writing to and reading from the nonvolatile memories of respective channels. The error correction controller is configured to use inter-channel error correction codes during any read process, performing inter-channel correction process on those of the data items read under the control of the channel controller, which have been designated. The additional correction module is configured to designate, in accordance with errors detected by the channel controller, data items to additionally correct, and to notify the data items so designated to the error correction controller while the channel controller is reading the data necessary in the inter-channel correction process.

#An embodiment will be described with reference to the accompanying drawings.

Facts

Application

13/301,335Filed 21 Nov 2011

Priority

JP 2011-01417826 Jan 2011

Published

US 2012/0192032 A126 Jul 2012

Granted

29 Apr 2014

Term ends

23 Mar 2032

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 123 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification4 codes

G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
G11C 2029/0411
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: online error correction
G06F
Computing and data processing
G11C
Static stores

Timeline

26 Jan 2011Priority claimedJP 2011-014178
21 Nov 2011Application filedUS 13/301,335
21 Nov 2011Assigned to Kabushiki Kaisha Toshibaassignment of assignor's interest
26 Jul 2012PublishedUS 2012/0192032 A1
29 Apr 2014GrantedUS 8,713,410 B2
12 Oct 2026TodayWithin its term
23 Mar 2032Term endsEstimated, includes 123 days of adjustment

Data storage apparatus, memory control apparatus and method for controlling flash memories

Life of this patent

Data storage apparatus, memory control apparatus and method for controlling flash memories

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims11

Description4,473 words

Drawings

Classification4 codes

Life of this patent

Description4,473 words