Bit error mitigation
AssigneeXilinx, Inc.
InventorsChen W. Tseng, Weiguang Lu, Christopher Y. Karman
Life of this patent
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Abstract
Approaches for mitigating single event upsets (SEUs) in a circuit arrangement. In response to each bit error of a plurality of bit errors, an error address indicative of the bit error in a configuration memory cell in the circuit arrangement is translated into a non-volatile memory address. A partial bitstream at the non-volatile memory address is read from a non-volatile memory. Successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to first and second internal configuration ports. A subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, is reconfigured with the partial bitstream.
Claims20
A method of mitigating single event upsets (SEUs) in a circuit arrangement, comprising:
- in response to each bit error of a plurality of bit errors, performing operations including:
- translating an error address indicative of the bit error in a configuration memory cell in the circuit arrangement into a non-volatile memory address;
- reading a partial bitstream at the non-volatile memory address in a non-volatile memory;
- alternately transmitting the partial bitstream to one of a first internal configuration port or a second internal configuration port of the circuit arrangement, wherein successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to the first and second internal configuration ports;
- and
- reconfiguring a subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, with the partial bitstream.
A circuit arrangement, comprising:
- a configuration memory;
- programmable resources coupled to the configuration memory;
- a first internal configuration port coupled to the configuration memory;
- a second internal configuration port coupled to the configuration memory;
- a memory interface;
- a decoder circuit coupled to the first and second internal configuration ports and to the memory interface, wherein the decoder circuit is configured and arranged to, in response to each bit error of a plurality of bit errors:
- translate an error address indicative of the bit error in a configuration memory cell in the configuration memory into a non-volatile memory address;
- read a partial bitstream via the memory interface at the non-volatile memory address in a non-volatile memory;
- and
- transmit the partial bitstream to one of the first or second internal configuration ports, wherein successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to the first and second internal configuration ports;
- and
- wherein each of the first and second internal configuration ports is configured and arranged to reconfigure a subset of configuration memory cells of the configuration memory, including the configuration memory cell referenced by the error address, in response to a partial bitstream received from the decoder.
A method of mitigating single event upsets (SEUs) in a circuit arrangement, comprising:
- activating a first decoder and deactivating a second decoder in the circuit arrangement;
- in response the first decoder being active and in response to each bit error of a plurality of bit errors performing, by the first decoder, operations including:
- translating an error address indicative of the bit error in a configuration memory cell in the circuit arrangement into a non-volatile memory address;
- reading a partial bitstream at the non-volatile memory address in a non-volatile memory;
- transmitting the partial bitstream to a first internal configuration port of the circuit arrangement;
- and
- in response to detecting a threshold number of bit errors in one configuration memory cell, deactivating the first decoder and activating the second decoder;
- in response to the second decoder being active and in response to each bit error of a plurality of bit errors performing, by the second decoder, operations including:
- translating an error address indicative of the bit error in a configuration memory cell in the circuit arrangement into a non-volatile memory address;
- reading a partial bitstream at the non-volatile memory address in the non-volatile memory;
- and
- transmitting the partial bitstream to a second internal configuration port of the circuit arrangement;
- and
- reconfiguring a subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, with each partial bitstream.
Dependencies are inferred from the claim text.