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US 8,713,407 B2Granted
Semiconductor memory system having ECC circuit and controlling method thereof
AssigneeHynix Semiconductor Inc.
InventorJun Rye Rho
Life of this patent
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Abstract
A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.
Claims11
A semiconductor memory system comprising:
- a memory area comprising a plurality of cells;
- and
- an error-correcting code (ECC) circuit in communication with the memory area,
- wherein the ECC circuit is configured to generate a first parity by correcting cell data of the memory area and a second parity by encoding corrected data of the cell data and to determine whether the cell data exceeds an error correction range or not by comparing the first parity and the second parity in a read mode.
1 more element
A method for controlling a semiconductor memory system, comprising:
- generating a first parity according to an encoding result in a write mode;
- reading and encoding corresponding cell data to generate a second parity in a read mode;
- primarily comparing the first parity with the second parity;
- tracking an error location according to a comparison result;
- correcting an error of the corresponding cell data according to the error location tracking result, and generating a third parity according to a correcting result;
- encoding corrected data to generate a fourth parity;
- and
- secondarily comparing the third parity with the fourth parity.
5 more elements
Dependencies are inferred from the claim text.