Erasing a non-volatile memory (NVM) system having error correction code (ECC)
AssigneeFreescale Semiconductor, Inc.
InventorsFuchen Mu, Frank K. Baker, Jr., Chen He
Life of this patent
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Abstract
A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.
Claims20
A semiconductor memory storage device, comprising:
- an array of non-volatile memory (NVM) bit cells, wherein the array of NVM bit cells is partitioned in one or more blocks;
- a memory controller coupled to the array of NVM bit cells;
- and
- an error correction code (ECC) unit coupled to the array and the memory controller, wherein the memory controller is configured to:
- during an erase operation on one of the one or more blocks,
- when a first verify operation detects only one of the NVM bit cells fails to erase verify at a normal erase verify voltage level, and
- when a second verify operation detects one of the NVM bit cells fails to erase verify at a relaxed erase verify voltage level, wherein the relaxed erase verify voltage level is higher than the normal erase verify voltage level, consider the erase operation to be successful.
A method of erasing a semiconductor memory device comprising:
- performing an erase operation on a subset of an array of non-volatile bit cells, and
- if during the erase operation a first erase verify operation detects only one of the non-volatile bit cells fails to erase verify at a normal erase verify voltage level and a second verify operation detects all of the non-volatile bit cells successfully erase at a relaxed erase verify voltage level, wherein the relaxed erase verify voltage level is higher than the normal erase verify voltage level, designating the erase operation as successful if a maximum number of erase pulses is reached.
A method of erasing a non-volatile semiconductor memory device comprising:
- determining a number of bit cells that failed to erase verify during an erase operation, wherein the bit cells are included in a subset of bit cells in an array of bit cells;
- determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells;
- and
- allowing the erase operation to be considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.
Dependencies are inferred from the claim text.