Device for increasing chip testing efficiency and method thereof

A method of increasing chip testing efficiency, the method comprising:

• utilizing a pattern generator to write a first logic voltage to at least one first bank of a plurality of first banks of a memory chip, and to write a logic voltage opposite to the first logic voltage to other first banks simultaneously;
• utilizing the pattern generator to write a second logic voltage to at least one second bank of a plurality of second banks of the memory chip, and to write a logic voltage opposite to the second logic voltage to other second banks simultaneously;
• utilizing a reading unit to read logic voltages stored in all memory cells of each bank of the memory chip;
• utilizing a logic operation circuit to execute a first logic operation on the logic voltages stored in all the memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank;
• and
• utilizing the logic operation circuit to execute a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip.

A method of increasing chip testing efficiency, the method comprising:

• utilizing a pattern generator to write a first logic voltage to at least one bank of a plurality of banks of a memory chip, and to write a logic voltage opposite to the first logic voltage to other banks of the plurality of banks simultaneously;
• utilizing a reading unit to read logic voltages stored in all memory cells of each bank of the memory chip;
• utilizing a logic operation circuit to execute a first logic operation on the logic voltages stored in all the memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank;
• and
• utilizing the logic operation circuit to execute a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip.

A device for increasing chip testing efficiency, the device comprising:

• a pattern generator for writing a logic voltage to each bank of a memory chip;
• a reading unit for reading logic voltages stored in all memory cells of each bank of the memory chip;
• a logic operation circuit for executing a first logic operation on the logic voltages stored in all the memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip;
• and
• a judgment unit for determining whether the memory chip is passed according to the second logic operation result.