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US 8,713,385 B2Granted
Error scanning in flash memory
AssigneeMicron Technology, Inc.
InventorsWilliam Henry Radke, Peter Sean Feeley, Siamack Nemazie
Life of this patent
Estimating the term…
Abstract
Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
Claims27
An apparatus comprising:
- a storage device in a memory controller to store a condition to scan for errors in information stored in a memory array of a memory device coupled to the memory controller, wherein the condition to scan is based on a number of accesses to cells of the memory device, wherein the memory controller is separated from the memory device;
- and
- a component to scan for errors in the information when the condition is met.
An apparatus comprising:
- a storage device in a memory controller to store a condition to scan for errors in information stored in a memory array of a memory device coupled to the memory controller, wherein the condition to scan is based on a number of accesses to cells of the memory device;
- and
- a component to scan for errors in the information when the condition is met, wherein the number of accesses comprises a number of read operations.
An apparatus comprising:
- a storage device in a memory controller to store a condition to scan for errors in information stored in a memory array of a memory device coupled to the memory controller, wherein the condition to scan is based on a number of accesses to cells of the memory device;
- and
- a component to scan for errors in the information when the condition is met, wherein the condition to scan being based on a number of accesses to cells of the memory device comprises the condition to scan being based on a number of accesses to cells of the entire memory array.
An apparatus comprising:
- a storage device in a memory controller to store a condition to scan for errors in information stored in a memory array of a memory device coupled to the memory controller, wherein the condition to scan is based on a number of accesses to cells of the memory device;
- and
- a component to scan for errors in the information when the condition is met, wherein the condition to scan being based on a number of accesses to cells of the memory device comprises the condition to scan being based on a number of sectors read in the memory array.
An apparatus comprising:
- a storage device in a memory controller to store a condition to scan for errors in information stored in a memory array of a memory device coupled to the memory controller, wherein the condition to scan is based on a number of accesses to cells of the memory device;
- and
- a component to scan for errors in the information when the condition is met, wherein the condition to scan being based on a number of accesses to cells of the memory device comprises the condition to scan being based on a total number of read operations performed on sectors of more than one block of the memory device.
An apparatus comprising:
- a storage device in a memory controller to store a condition to scan for errors in information stored in a memory array of a memory device coupled to the memory controller, wherein the condition to scan is based on a number of accesses to cells of the memory device;
- and
- a component to scan for errors in the information when the condition is met, wherein the component to scan for errors in the information comprises a component to scan the entire memory device for errors.
An apparatus comprising:
- a storage unit in a processor to store a condition to scan for errors in information stored in a memory array of a memory device, wherein the condition to scan is based on a number of accesses to cells of the memory device, wherein the processor is separated from the memory device;
- and
- a component to scan for errors in the information when the condition is met.
Dependencies are inferred from the claim text.