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US 8,713,379 B2Granted
System and method of interfacing co-processors and input/output devices via a main memory system
AssigneeDiablo Technologies Inc.
InventorsMichael L. Takefman, Maher Amer, Riccardo Badalone
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Abstract
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
Claims13
A computer apparatus comprising:
- an interface configured to communicate with a host system via a memory controller on the host system to receive bit-interleaved data that is interleaved using an unknown interleave mapping;
- a data de-interleaver configured to:
- solve for the unknown interleave mapping associated with the bit-interleaved data to determine a mapping solution, and
- de-interleave the bit-interleaved data based on the mapping solution to generate de-interleaved data;
- and
- a processing unit configured to process the de-interleaved data.
3 more elements
A method for descrambling data received from a host system, comprising the steps of:
- solving for an unknown scramble sequence, based on which the data is scrambled by the host system, by:
- instructing the computer system to write a zero data pattern to address zero to generate a first scrambled data value;
- storing the first scrambled data value as one of the scramble generator vectors;
- and
- for each one signal in the set of address signals,
- setting only the one signal to “1” value while other signals in the set of address signals are set to “0” value,
- writing a zero data pattern to an address corresponding to the address signals to generate a second scrambled data value,
- performing a bitwise XOR operation of the first scrambled data value and the second scrambled data value to generate a scramble generator vector associated with the one of the address signals,
- storing the scramble generator vector associated with the one of the address signals;
- and
- performing a bitwise XOR operation of the scramble sequence and the data.
8 more elements
Dependencies are inferred from the claim text.