Non-intrusive processor tracing
AssigneeApple Inc.
InventorsTimothy J. Millet, Shun Wai (“Dominic”) Go, Conrad H. Ziesler
Life of this patent
Estimating the term…
Abstract
A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.
Claims21
An apparatus comprising:
- a memory controller comprising a plurality of ports, wherein the memory controller is configured to receive memory requests on each port of the plurality of ports;
- one or more processors coupled to a first port of the plurality of ports of the memory controller;
- and
- a direct memory access (DMA) controller coupled to a second port of the plurality of ports of the memory controller, and coupled to a third port of at least one of the one or more processors, the second port being different from the first port;
- wherein the DMA controller is coupled to read trace data from the one or more processors via a third port, and convey corresponding trace data to the memory controller via the second port.
An apparatus comprising:
- a bus interface unit (BIU) comprising a trace buffer;
- a processor configured to write trace data to the trace buffer;
- a direct memory access (DMA) controller configured to read trace data from the trace buffer via a first port;
- and
- a memory controller coupled to the processor via a second port, and coupled to the DMA controller via a third port, wherein the second port is different from the third port;
- wherein the BIU is configured to:
- monitor a fill level of the trace buffer;
- reduce a frequency of a clock coupled to the processor responsive to detecting the fill level exceeds a first threshold;
- and
- increase a frequency of the clock responsive to detecting the fill level has fallen below a second threshold.
A method for use in a computing system, the method comprising:
- generating trace data at one or more processors;
- storing the trace data in one or more trace buffers;
- the one or more processors conveying memory requests to a memory controller via a real-time port;
- a direct memory access (DMA) controller reading the trace data from the one or more trace buffers via a DMA port;
- and
- writing the trace data from the DMA controller to a non-real-time port of the memory controller, wherein the real-time port is different from the non-real-time port.
A system comprising:
- a processor complex comprising one or more processors and a bus interface unit (BIU);
- a non-real-time (NRT) block comprising a direct memory access (DMA) controller;
- and
- a memory controller comprising a plurality of ports, wherein the memory controller is coupled to the processor complex via a first port of the plurality of ports, and the memory controller is coupled to the non-real-time block via a second port of the plurality of ports, wherein the first port is different from the second port;
- wherein the processor complex is configured to:
- capture trace data corresponding to the one or more processors;
- and
- store the trace data in one or more trace buffers;
- wherein the DMA controller is configured to:
- read trace data from the one or more trace buffers;
- and
- write trace data to the memory controller via a non-real-time port of the memory controller.
Dependencies are inferred from the claim text.