Semiconductor apparatus

A semiconductor apparatus comprising:

• a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal and generate a first chip ID signal and a converted enable signal;
• a second chip ID generation unit configured to receive the converted enable signal through a second through-silicon via and the clock signal to generate a second chip ID signal;
• a selection ID generation unit configured to provide one of the first chip ID signal and a first replacement ID signal as a first selection ID signal and provide one of the second chip ID signal and a second replacement ID signal as a second selection ID signal;
• and
• a chip selection signal generation unit configured to receive the first and second selection ID signals and a main ID signal and generate first and second chip selection signals.

A semiconductor apparatus including first and second chips stacked, comprising:

• a first set of through-silicon vias configured to pass through and connect the first and second chips while extending along one straight line, and transmit a signal generated from a circuit disposed in the first chip;
• a first redistribution layer configured to electrically connect the first set of through-silicon vias and a circuit disposed in the second chip;
• and
• a second redistribution layer configured to electrically connect the circuit disposed in the second chip and the first set of through-silicon vias.

A semiconductor apparatus with a plurality of chips, comprising:

• a first circuit module configured to receive a chip enable signal and a clock signal and generate a first identification signal indicative of a first code representing a first chip of the plurality of chips and a delayed enable signal, the delayed enable signal being obtained by delaying the enable signal based on the clock signal;
• a second circuit module configured to receive the delayed enable signal from the first circuit module and the clock signal and generate a second identification signal indicative of a second code representing a second chip of the plurality of chips;
• a first chip designation module configured to receive the first identification signal and a chip designation signal indicative of a target code representing a target chip to be activated among the plurality of chips including the first and second chips, and compare the first code with the target code to generate a first chip selection signal based thereon;
• and
• a second chip designation module configured to receive the second identification signal indicative of a second code representing the second chip and the chip designation signal, and compare the second code with the target code to generate a second chip selection signal based thereon.