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US 8,713,347 B1Granted
Apparatus and method for masking a clock signal
AssigneeMarvell International Ltd.
InventorRoss Swanson
Life of this patent
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Abstract
A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock source. In one version, a memory controller configures a masking circuit to either allow a clock signal to the clock input or to mask the clock input from a bidirectional clock bus. The masking circuit may comprise a storage element and a gate, as an example.
Claims20
A method comprising:
- receiving, by a logic element, a clock signal from a clock bus in between a first high impedance state and a second high impedance state entered into by the clock bus, the clock signal cycling over a plurality of clock cycles, and the logic element being in communication with a clock input of an electronic component;
- and
- communicating a masking signal from a storage element to the logic element to mask the clock input of the electronic component from the clock bus, the masking signal being communicated in response to:
- a transition of a control signal received at a first input of the storage element from a first logic state to a second logic state, wherein the control signal is received over the plurality of clock cycles in between the first high impedance state and the second high impedance state, and wherein, over the plurality of clock cycles, the transition of the control signal occurs within one clock cycle of a final transition of the clock signal before the clock bus enters the second high impedance state, and wherein the control signal is maintained in the first logic state until the transition occurs;
- and
- the final transition of the clock signal received at a second input of the storage element.
3 more elements
A clock masking system comprising:
- a logic element in communication with a clock input of an electronic component, the logic element being configured to:
- receive a clock signal from a clock bus in between a first high impedance state and a second high impedance state entered into by the clock bus, wherein the clock signal cycles over a plurality of clock cycles;
- receive a masking signal that masks the clock input from the clock bus, and
- output at least one of the clock signal and a masked signal;
- and
- a storage element in communication with the logic element, the storage element being configured to:
- determine a transition of a control signal received at a first input of the storage element from a first logic state to a second logic state, wherein the control signal is received over the plurality of clock cycles, and wherein, over the plurality of clock cycles, the transition of the control signal occurs within one clock cycle of a final transition of the clock signal before the clock bus enters the second high impedance state, and wherein the control signal is maintained in the first logic state until the transition occurs;
- determine the final transition of the clock signal received at a second input of the storage element;
- and
- communicate the masking signal to the logic element in response to determining the transition of the control signal and the final transition of the clock signal.
7 more elements
Dependencies are inferred from the claim text.