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US 8,713,345 B2Granted
Apparatus with a local timing circuit that generates a multi-phase timing signal for a digital signal processing circuit
AssigneeSony Corporation
InventorTatsuya Sugioka
Life of this patent
Estimating the term…
Abstract
A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit.
Claims29
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a single phase clock signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the single phase clock signal, and
- wherein the digital signal processing circuit receives the single phase clock signal and the multi-phase timing signal, and uses the single phase clock signal for low processing speed operations and the multi-phase timing signal for high processing speed operations.
4 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit;
- and
- an additional digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a single phase clock signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the single phase clock signal, and
- wherein the digital signal processing circuit receives the multi-phase timing signal, and the additional digital signal processing circuit receives the single phase signal, with the single phase signal being used by the additional digital signal processing circuit for low processing speed operations and the multi-phase timing signal being used by the digital signal processing circuit for high processing speed operations.
5 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a phase locking pulse signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the phase locking pulse signal,
- wherein the local timing circuit comprises a plurality of delay elements that receive the control signal and produce the differential delay of the respective components of the multi-phase timing signal, and
- wherein the plurality of delay elements match delay elements of the reference timing circuit from which the control signal is received.
5 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a phase locking pulse signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the phase locking pulse signal,
- wherein the local timing circuit comprises a plurality of delay elements that receive the control signal and produce the differential delay of the respective components of the multi-phase timing signal,
- wherein the reference timing circuit comprises a phase locked loop circuit, and
- wherein the phase locking pulse signal is a clock output of the phase locked loop circuit, the local timing circuit comprises a ring buffer that includes the plurality of delay elements, and the control signal is a voltage or current control signal that is based upon a voltage or current control signal of the phase locked loop circuit.
6 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a phase locking pulse signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the phase locking pulse signal,
- wherein the local timing circuit comprises a plurality of delay elements that receive the control signal and produce the differential delay of the respective components of the multi-phase timing signal,
- wherein the reference timing circuit comprises a phase locked loop circuit, and
- wherein the phase locking pulse signal is a reference clock signal, the local timing circuit comprises a ring buffer that includes the plurality of delay elements, and the control signal is a voltage or current control signal that is based upon a voltage or current control signal of the phase locked loop circuit.
6 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a phase locking pulse signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the phase locking pulse signal,
- wherein the local timing circuit comprises a plurality of delay elements that receive the control signal and produce the differential delay of the respective components of the multi-phase timing signal,
- wherein the reference timing circuit comprises a phase locked loop circuit, and
- wherein the phase locking pulse signal is a clock output of the phase locked loop circuit, the local timing circuit comprises a ring buffer that includes the plurality of delay elements, the control signal is a voltage or current control signal that is based upon a voltage or current control signal of the phase locked loop circuit, and the digital signal processing circuit comprises a counter that receives the multi-phase timing signal.
6 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a phase locking pulse signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the phase locking pulse signal,
- wherein the local timing circuit comprises a plurality of delay elements that receive the control signal and produce the differential delay of the respective components of the multi-phase timing signal,
- wherein the reference timing circuit comprises a delay locked loop circuit, and
- wherein the phase locking pulse signal is a clock output of the delay locked loop circuit, the local timing circuit comprises a ring buffer that includes the plurality of delay elements, and the control signal is a voltage or current control signal that is based upon a voltage or current control signal of the delay locked loop circuit.
6 more elements
An electronic circuit, comprising:
- a digital signal processing circuit;
- a reference timing circuit that generates a reference timing signal;
- and
- a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit,
- wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit,
- wherein the reference timing signal comprises a phase locking pulse signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the phase locking pulse signal,
- wherein the local timing circuit comprises a plurality of delay elements that receive the control signal and produce the differential delay of the respective components of the multi-phase timing signal,
- wherein the reference timing circuit comprises a delay locked loop circuit, and
- wherein the phase locking pulse signal is a reference clock signal, the local timing circuit comprises a ring buffer that includes the plurality of delay elements, and the control signal is a voltage or current control signal that is based upon a voltage or current control signal of the delay locked loop circuit.
6 more elements
Dependencies are inferred from the claim text.