Methods and apparatus for clock signal synchronization in a configuration of series connected semiconductor devices

Abstract

A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices. The system controller further includes a detector for processing the first and second clock signals to detect a phase difference therebetween; and a synchronization controller for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference detected by the detector.

Dependencies are inferred from the claim text.