Method and apparatus for power management control of an embedded memory having sleep and shutdown features

A method of selecting a power control mode associated with a power management controller, the power management controller being operative to control a power mode associated with a memory device, the method comprising:

• selecting, by a processing device, a largest memory device size that is less than or equal to a total memory size;
• determining, by the processing device, whether the memory device associated with the selected memory device size satisfies chip select signal timing requirements;
• determining, by the processing device, whether the memory device associated with the selected memory device size satisfies timing requirements associated with a plurality of power control modes in response to determining that the memory device associated with the selected memory device size satisfies the chip select signal timing requirements;
• calculating, by the processing device, power consumed by the memory device associated with the selected memory device size in the plurality of power control modes in response to determining that the memory device associated with the selected memory device size satisfies the timing requirements associated with the plurality of power control modes;
• and
• selecting, by the processing device, that power control mode in which the memory device associated with the selected memory device size consumes a least amount of power.

An electronic system comprising:

• a processing device;
• a memory device operatively coupled to the processing device;
• and
• a power management controller operatively coupled to the processing device and memory device, the power management controller being configured to control a power mode associated with the memory device, the power management controller comprising at least one logic element operative to provide a power mode control signal, the at least one logic element being responsive to a control signal and a delayed control signal, the delayed control signal representing the control signal following a delay, the control signal being provided by the processing device, the power mode control signal transitioning (1) inactive before a chip select signal transitions active and (2) active after the chip select signal transitions inactive, the chip select signal being operative to control the memory device, the power mode control signal being operative to control the power mode associated with the memory device.