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US 8,713,335 B2Granted
Parallel processing computer systems with reduced power consumption and methods for providing the same
AssigneeCognitive Electronics, Inc.
InventorsAndrew C. Felch, Richard H. Granger
Life of this patent
Estimating the term…
Abstract
A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.
Claims18
A parallel processing computing system comprising:
- (a) an ordered set of m memory banks including a first and a last memory bank, wherein m is an integer greater than 1;
- and
- (b) a processor core that implements (i) n virtual processors, (ii) a pipeline having p ordered stages, including a memory operation stage, and (iii) a virtual processor selector function,
- wherein n is an integer greater than 1 and p is an integer greater than 1 and less than or equal to n,
- wherein the memory banks are the most local data memory to the processor core, wherein the processor core clock speed is faster than the memory access rate of the memory banks by an integer multiple,
- wherein each virtual processor is assigned in order to one of the memory banks in order,
- wherein after the last memory bank is assigned, the next virtual processor is assigned to the first memory bank,
- wherein the multiple virtual processors and their respective memory banks are adapted to simultaneously execute independent threads, and each virtual processor is adapted to execute pipeline stages in order, and no virtual processor executes the same pipeline stage as any other virtual processor at the same time, and
- wherein the next virtual processor to begin the pipeline is chosen by the virtual processor selector function.
6 more elements
A parallel processing computing system comprising:
- (a) an ordered set of m memory banks including a first and a last memory bank, wherein m is an integer greater than 1;
- and
- (b) a processor core that implements (i) n virtual processors, (ii) a pipeline having p ordered stages, including a memory operation stage, and (iii) a virtual processor selector function,
- wherein n is an integer greater than 1, and p is an integer greater than 1 and less than or equal to n,
- wherein the memory banks are the most local data memory to the processor core, wherein the processor core clock speed is faster than the memory access rate of the memory banks by an integer multiple,
- wherein each virtual processor is assigned in order to one of the memory banks in order,
- wherein after the last memory bank is assigned, the next virtual processor is assigned to the first memory bank,
- wherein the n virtual processors and their respective memory banks are adapted to simultaneously execute independent threads, and each virtual processor is adapted to execute pipeline stages in order, and no virtual processor executes the same pipeline stage as any other virtual processor at the same time, and
- wherein the next virtual processor to begin the pipeline is chosen by the virtual processor selector function such that the next virtual processor does not have any pipeline hazards.
6 more elements
Dependencies are inferred from the claim text.