Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit

A device comprising:

• an input/output terminal;
• an input/output circuit coupled to the input/output terminal and receiving an On Die Termination (ODT) signal, the input/output circuit performing an ODT operation when the ODT signal is activated;
• and
• a clock generating circuit receiving a first clock signal and outputting an internal clock signal in response to the first clock signal, the internal clock signal being substantially equal in frequency to the first clock signal, the clock generating circuit comprising a coarse delay line, a fine delay line and a selector circuit, the coarse delay line being greater in adjustment pitch than the fine delay line,
• the coarse delay line comprising:
• a first input node, which receives the first clock signal;
• and
• a first output node connected to the fine delay line and the selector,
• the fine delay line comprising:
• a second input node connected to the first output node of the coarse delay line;
• and
• a second output node connected to the selector,
• the selector circuit comprising:
• a third input node coupled to the first output node;
• a fourth input node coupled to the second output node;
• a fifth input node which receives the ODT signal;
• and
• a third output node, which outputs the internal clock,
• wherein the selector circuit receives the ODT signal and connects the third input node to the third output node when the ODT signal is activated and connects the fourth input node to the third output node when the ODT signal is not activated.