Fast and compact circuit for bus inversion
AssigneeRound Rock Research, LLC
InventorMayur Joshi
Life of this patent
Estimating the term…
Abstract
A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.
Claims24
A processing system comprising:
- at least one processor coupled to a bus;
- at least one memory controller coupled to the bus;
- at least one primary bus bridge coupled to the bus;
- wherein the memory controller is coupled to at least one memory bus and the primary bus bridge is coupled to at least one peripheral bus;
- wherein at least one of the processor, memory controller or primary bus bridge comprises a bus inversion circuit further comprising:
- an advantage function circuit, adapted to input bits to be transmitted over a bus, the advantage function circuit adapted to calculate an advantage of inversion and an advantage of non-inversion for each input bit and being adapted to calculate an advantage of inversion and an advantage of non-inversion for at least one inversion bit to be transmitted over the bus;
- and
- a majority voter circuit for determining whether a plurality of bits to be transmitted over a bus should be inverted before being transmitted based on advantages received from the advantage function circuit;
- wherein the majority voter circuit provides two outputs, a first output corresponding to advantages of inversion and a second output corresponding to advantages of non-inversion.
Dependencies are inferred from the claim text.