Heap/stack guard pages using a wakeup unit

A computer program product for memory access checking on a computer system, said computer program product comprising a computer readable medium, the computer readable medium not only a propagating signal, said computer readable medium having recorded therein computer readable instructions for:

• invalidating memory ranges within a first level cache memory in the memory device, the invalidated first level cache memory ranges in the memory device corresponding to a guard page, and said guard page being moved subject to a top of heap size change, the invalidating of memory ranges being executed by an operating system;
• configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers;
• selecting one of the plurality of WAC registers using the operating system;
• setting up the selected WAC register related to the invalidated memory ranges corresponding to said guard page using the operating system;
• configuring a wakeup unit to interrupt on access of the selected WAC register using the operating system;
• detecting access of the memory device between said level-1 cache and a second level cache memory using the wakeup unit when a guard page is violated;
• generating an interrupt to the core using the wakeup unit;
• querying the wakeup unit using the operating system when the interrupt is generated to determine the source of the interrupt;
• detecting the activated WAC registers assigned to the violated guard page;
• and
• initiating a response using the operating system after detecting the activated WAC registers.

A system for providing memory access checking on a processor, comprising:

• a computer system including a data storage device, the computer system including a program stored in the data storage device and steps of the program being executed by a processor;
• a memory device including level-1 cache;
• an operating system for invalidating level-1 cache ranges corresponding to a guard page, and said guard page being moved subject to a top of heap size change;
• a plurality of wakeup address compare (WAC) registers being configured to allow access to selected WAC registers, one of the plurality of WAC registers being selected using the operating system;
• a WAC register being related to invalidated memory ranges corresponding to the guard page;
• a wakeup unit interrupting on access of the selected WAC register using the operating system, the wakeup unit detecting access of the memory device between said level-1 cache and a second level cache memory when a guard page is violated;
• an interrupt being generated to the core using the wakeup unit;
• the source of the interrupt being determined by querying the wakeup unit using the operating system when the interrupt is generated;
• and
• a response initiated by the operating system after detecting activated WAC registers when access of the memory device is detected using the wakeup unit when the guard age page is violated.