Register files for a digital signal processor operating in an interleaved multi-threaded environment

A multithreaded processor device comprising:

• a plurality of instruction caches, each instruction cache is associated with a separate program thread;
• a sequencer sequentially fetching instructions from the plurality of instruction caches;
• a plurality of instruction execution units responsive to the sequencer;
• and
• a first register file including a first plurality of registers, the first register file coupled to each of the plurality of instruction execution units, the first register file supporting execution of a first program thread to be executed, and associated with one of the plurality of instruction caches, the first register file including data read ports, the plurality of instruction execution units configured to access the first register file more times than the number of data read ports within a period of time before the next sequential fetching of instructions from the one of plurality of instruction caches.

A portable communication device, comprising:

• a digital signal processor;
• wherein the digital signal processor includes:
• a memory;
• a sequencer responsive to the memory to fetch a program instruction having a number of operands;
• at least one instruction execution unit responsive to the sequencer;
• and
• a plurality of register files coupled to the at least one instruction execution unit, each of the plurality of register files including no more than four data read ports and wherein the number of operands is greater than four.

An audio file player, comprising:

• a digital signal processor;
• an audio coder/decoder (CODEC) coupled to the digital signal processor;
• a multimedia card coupled to the digital signal processor;
• a universal serial bus (USB) port coupled to the digital signal processor;
• and
• wherein the digital signal processor includes:
• a memory;
• a sequencer responsive to the memory to fetch a program instruction having a number of operands;
• at least one instruction execution unit responsive to the sequencer;
• and
• a plurality of register files coupled to the at least one instruction execution unit, each of the plurality of register files including no more than four data read ports and wherein the number of operands is greater than four.