Address generation unit for accessing a multi-dimensional data structure in a desired pattern

A method comprising:

• providing a read and write capable data memory storing a multi-dimensional data structure, and a at least one processor;
• providing a programmable address generation unit comprising programmable descriptor memory, said programmable address generation unit configured to translate connection identifiers into real addresses in order to access the multi-dimensional data structure in a desired pattern;
• wherein said programmable descriptor memory further comprises a buffer descriptor memory, and said buffer descriptor memory programmable to implement any of point-to-point, broadcast, scatter, and gather buffer types;
• and
• wherein said descriptor memory further comprises a port descriptor memory, and said port descriptor memory is programmable to implement any of FIFO, matrix transform, nested loop, end point, and non-recursive pattern port types;
• configuring the address generation unit to calculate the real addresses by using said at least one processor to load at least one descriptor for a pattern into said port descriptor memory;
• wherein said connection identifier comprises a predefined number of bits, and said at least one processor further programs the address generation unit by loading said connection identifier into said buffer descriptor memory;
• and accessing the multi-dimensional data structure at the real addresses calculated by the address generation unit using said descriptor for a pattern and said connection identifier.

An apparatus comprising:

• a read and write capable data memory capable of storing a multi-dimensional data structure, and at least one non-address-generation-unit processor;
• a programmable address generation unit configured to translate connection identifiers into real addresses in order to access said multi-dimensional data structure in a desired pattern in said data memory,
• wherein the address generation unit comprises programmable descriptor memory, and further comprises at least one custom VLSI circuit or gate array, or at least one programmable address generation unit processor, or at least one programmable hardware device selected from the group consisting of field programmable gate arrays, programmable array logic, and programmable logic devices;
• wherein said programmable descriptor memory further comprises a buffer descriptor memory, and said buffer descriptor memory is selected from the group consisting of point-to-point, broadcast, scatter, and gather buffer types;
• and
• wherein said descriptor memory further comprises a port descriptor memory, and said port descriptor memory is selected from the group consisting of FIFO, matrix transform, nested loop, end point, and non-recursive pattern port types;
• the address generation unit configured to calculate the real addresses by executing a series of patterns pre-programmed by said at least one non-address-generation-unit processor into the address generation unit's port descriptor memory prior to accessing said multi-dimensional data structure, the address generation unit receiving as inputs from said at least one non-address-generation-unit processor, a set of descriptors defining characteristics of said pattern;
• wherein said connection identifier comprises a predefined number of bits, and said at least one non-address-generation-unit-processor loads said connection identifier into said buffer descriptor memory;
• wherein said non-address-generation-unit processor is configured to access the multi-dimensional data structure at the real addresses calculated by the address generation unit based upon said descriptor for a pattern and said connection identifier.