US 8,713,284 B1 · Methods and apparatus for address translation functions

Abstract

Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. An address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power.

Claims21

Dependent claims

A method comprising:

receiving a sequence of addresses in a storage unit from a processor external to the storage unit, the storage unit configured to access data according to translation information stored in the storage unit indicating that each received address of the sequence of addresses is to be operated on and converted to a translated address for accessing the data from a memory within the storage unit;
translating within the storage unit each received address to a translated address according to the translation information;
and
accessing the data at the translated address from the memory within the storage unit for output from the storage unit, wherein the translation information is in the form of a k by (k+1) bit matrix of parameters that are logically combined with each received address of k bits generating a translated form of the received address as the translated address.

1 more element

A method comprising:

receiving a first communication instruction that is decoded in a first processing element (PE) and a second communication instruction that is separately decoded in a second PE, wherein the first communication instruction is configured with a first target operand k bit address and the second communication instruction is configured with a second target operand k bit address;
reading a first data element from a first register file memory located in the first PE to be communicated to a second PE in response to the first communication instruction;
translating the second target operand k bit address in the second PE by combining a k by (k+1) bit matrix of second PE parameters with the second target operand k bit address to generate a translated second PE target address;
and
storing the first data element received in the second PE at the translated second PE target address in a second register file memory located in the second PE.

2 more elements

Dependencies are inferred from the claim text.

Methods and apparatus for address translation functions

Life of this patent

Methods and apparatus for address translation functions

Life of this patent

Abstract

Claims21