Critical word forwarding with adaptive prediction

A method comprising:

• receiving, in an interface unit, an indication from a memory controller that an initial word of a cache block fill is predicted to be provided from the memory controller to the interface unit;
• the interface unit predicting a subsequent clock cycle at which a request to forward the initial word to a processor that initiated the cache block fill is to be generated in order to transmit the initial word in the case that the initial word is provided as expected according to the prediction from the memory controller, wherein the interface unit predicting the subsequent clock cycle is in response to the indication from the memory controller, and wherein the subsequent clock cycle is predicted because uncertainties in the delay in delivering the initial word cause the delay to vary for different cache block fills from the same memory controller, during use, and wherein the interface unit operates according to a first clock, and wherein the memory controller operates according to a second clock that is asynchronous to the first clock, wherein a cause of the uncertainty in the delay includes a synchronization from a second clock domain associated with the second clock to a first clock domain associated with the first clock;
• generating the request in the subsequent clock cycle in response to the interface unit predicting the subsequent clock cycle;
• receiving a grant in response to the request;
• detecting that the initial word is provided as predicted by the memory controller;
• and
• forwarding the initial word in response to the grant.

An integrated circuit comprising:

• one or more processors, each processor comprising a data cache and configured to generate read operations in response to cache misses in the data cache;
• a second level cache coupled to the processors and configured to transmit one or more of the read operations to an interface unit, wherein the one or more read operations miss in the second level cache;
• and
• the interface unit coupled to the second level cache and to a memory controller, wherein the interface unit is configured to transmit the one or more read operations to the memory controller, and wherein the interface unit is coupled to receive an early response from the memory controller, and wherein the interface unit is configured to predict a subsequent clock cycle at which a critical word of a cache block will be available for forwarding for a given read operation of the one or more read operations in response to the early response corresponding to the given read operation, and wherein the interface unit is configured to monitor delays between early responses and corresponding critical words to modify the prediction for subsequent read operations based on the detected delays, and wherein the subsequent clock cycle is predicted because uncertainties in the delay cause the delay to vary for different read operations directed to the same memory controller, and wherein the interface unit is configured to operate according to a first clock, and wherein N is measured in clock cycles of the first clock, and wherein the memory controller is configured to operate according to a second clock that is asynchronous to the first clock, wherein a cause of the uncertainty in the delay includes a synchronization from a second clock domain associated with the second clock to a first clock domain associated with the first clock.