Managing a spinlock indicative of exclusive access to a system resource
AssigneeNVIDIA Corporation
InventorsMark A. Overby, Andrew Currid
Life of this patent
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Abstract
One embodiment of the present invention sets forth a technique for synchronization between two or more processors. The technique implements a spinlock acquire function and a spinlock release function. A processor executing the spinlock acquire function advantageously operates in a low power state while waiting for an opportunity to acquire spinlock. The spinlock acquire function configures a memory monitor to wake up the processor when spinlock is released by a different processor. The spinlock release function releases spinlock by clearing a lock variable and may clear a wait variable.
Claims16
A method for managing a spinlock to indicate exclusive access to a system resource, the method comprising:
- upon determining that a first processor is attempting to acquire the spinlock, raising an execution priority level associated with the first processor from an initial priority level to a high priority level;
- configuring a monitor circuit associated with the first processor to monitor a memory address associated with spinlock state data;
- testing a lock flag associated with the spinlock state data and determining that the spinlock is in a locked state;
- waiting in a low power state until the memory address is accessed by a second processor by executing a memory wait operation that causes the first processor to enter the low power state and subsequently exit the low power state when the memory address is accessed by the second processor;
- testing the lock flag associated with the spinlock state data and determining that the spinlock is no longer in the locked state;
- indicating that the system resource is capable of being exclusively accessed by the first processor;
- clearing the lock flag to indicate that the spinlock has been released from the first processor;
- and
- upon determining that the spinlock has been released from the first processor, setting the priority level of the first processor back to the initial priority level.
A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to manage a spinlock configured to indicate exclusive access to a system resource by performing the steps:
- upon determining that a first processor is attempting to acquire the spinlock, raising an execution priority level associated with the first processor from an initial priority level to a high priority level;
- configuring a monitor circuit associated with the first processor to monitor a memory address associated with spinlock state data;
- testing a lock flag associated with the spinlock state data and determining that the spinlock is in a locked state;
- waiting in a low power state until the memory address is accessed by a second processor by executing a memory wait operation that causes the first processor to enter the low power state and subsequently exit the low power state when the memory address is accessed by the second processor;
- testing the lock flag associated with the spinlock state data and determining that the spinlock is no longer in the locked state;
- indicating that the system resource is capable of being exclusively accessed by the first processor;
- clearing the lock flag to indicate that the spinlock has been released from the first processor;
- and
- upon determining that the spinlock has been released from the first processor, setting the priority level of the first processor back to the initial priority level.
A computing device, comprising:
- a memory system;
- a first monitor circuit coupled to the memory system;
- and
- a first processor coupled to the memory system and the first monitor circuit, and configured to:
- upon determining that a spinlock is to be acquired, raise an execution priority level associated with the first processor from an initial priority level to a high priority level;
- configure a monitor circuit associated with the first processor to monitor a memory address associated with spinlock state data;
- test a lock flag associated with the spinlock state data and determining that the spinlock is in a locked state;
- wait in a low power state until the memory address is accessed by a second processor by executing a memory wait operation that causes the first processor to enter the low power state and subsequently exit the low power state when the memory address is accessed by the second processor;
- test the lock flag associated with the spinlock state data and determine that the spinlock is no longer in the locked state;
- indicate that the system resource is capable of being exclusively accessed by the first processor;
- clear the lock flag to indicate that the spinlock has been released from the first processor;
- and
- upon determining that the spinlock has been released from the first processor, set the priority level of the first processor back to the initial priority level.
Dependencies are inferred from the claim text.