Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance

An apparatus comprising:

• a processor having an execution unit including a first core and a second core;
• a last level cache (LLC) shared by the first and second cores;
• a power control unit (PCU) to reduce an amount of power supplied to the LLC and to the processor, based on a reduced amount of the LLC being used by the processor and to monitor the LLC to identify the reduced amount of the LLC being used by the processor to process data;
• a finite state machine (FSM) the FSM to reduce an amount of the LLC available for use by the processor, based on a cache size control signal received from the PCU, the cache size control signal based on the reduced amount of the LLC being used.

A system comprising:

• a computing device having a processor and memory, the processor coupled to the memory to process data stored in the memory;
• the processor having an execution unit including a first core and a second core that share a last level cache (LLC);
• the execution unit coupled to a power control unit (PCU) and to a finite state machine (FSM), the FSM coupled to the power control unit;
• monitor code of the power control unit to monitor the cache to identify a reduced amount of cache being used by the processor to process data;
• the FSM to reduce an amount of cache available for use by the processor, based on a cache size control signal received from the power control unit, the cache size control signal based on the reduced amount of cache being used;
• the power control unit to reduce an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used.