Memory device and method for dynamic random access memory having serial interface and integral instruction buffer
AssigneeNokia Corporation
InventorsEero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link.
Claims23
A method, comprising:
- receiving a plurality of memory access instructions over a serial interconnect at a dynamic random access memory integrated circuit;
- buffering the plurality of memory access instructions in the dynamic random access memory integrated circuit;
- and
- executing the buffered memory access instructions;
- wherein the plurality of memory access instructions comprise at least one command;
- and
- wherein, in response to a first memory access instruction of the buffered plurality of memory access instructions and a second memory access instruction of the buffered plurality of memory access instructions both referencing a same page of the dynamic random access memory integrated circuit, and the first memory access instruction being non-sequential with respect to the second memory access instruction, the dynamic random access memory integrated circuit executing the buffered plurality of memory access instructions in a different order than the order in which they are received.
A dynamic random access memory integrated circuit, comprising:
- an interface to a serial interconnect, said interface configured to receive a plurality of memory access instructions over the serial interconnect;
- and
- a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit;
- wherein the plurality of memory access instructions comprise at least one command;
- and
- wherein, in response to a first memory access instruction of the buffered plurality of memory access instructions and a second memory access instruction of the buffered plurality of memory access instructions both referencing a same page of the dynamic random access memory integrated circuit and the first memo access instruction being non-sequential with respect to the second memory access instruction, the dynamic random access memo integrated circuit executing the buffered plurality of memory access instructions in a different order than the order in which they are received.
Dependencies are inferred from the claim text.