Memory device program window adjustment
AssigneeMicron Technology, Inc.
InventorsVishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
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Abstract
In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
Claims20
A memory device comprising:
- an array of memory cells;
- and
- control circuitry configured to control the memory device, the control circuitry configured to read erase threshold voltage of memory cells in a group of memory cells, identify a maximum erase threshold voltage for each memory cell in the group, generate a program level conversion table in response to the maximum erase threshold voltages, the control circuitry further configured to program reference memory cells in response to the conversion table.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry configured to read erase threshold voltages of memory cells in an erase block of memory cells, identify a maximum erase threshold voltage for each memory cell in the erase block, generate a program level conversion table in response to the maximum erase threshold voltages, the control circuitry further configured to program reference memory cells in response to the conversion table.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry configured to read erase threshold voltages of memory cells in a group of memory cells, identify a maximum erase threshold voltage for memory cells in the group, generate a conversion table in response to the maximum erase threshold voltages, the control circuitry further configured to control programming of reference memory cells in response to the conversion table.
Dependencies are inferred from the claim text.