Bus controller for handling split transactions
AssigneeNXP B.V.
InventorsYeow Khai Chang, Weng Fei Moo
Life of this patent
Estimating the term…
Abstract
A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.
Claims15
A device that executes split transactions, the device comprising:
- a host microprocessor;
- a system memory connected to the host microprocessor, wherein the host microprocessor transfers data to the system memory over a peripheral bus;
- a Universal Serial Bus (USB) host controller connected to the host microprocessor and the system memory, wherein the USB host controller retrieves the data from the system memory and comprises:
- an on-chip RAM connected to an interface, the on-chip RAM storing transfer descriptors sent from the host microprocessor,
- registers that support the RAM, and
- a host controller logic unit connected by an internal bus to the registers, wherein the USB host controller executes a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across the interface and the transfer involves an amount of data specified by the single transfer descriptor without intervention by the host microprocessor;
- wherein the single transfer descriptor handles both Start Split (SS) and Complete Split (CS) transactions.
A method of transferring Universal Serial Bus (USB) data with a host controller, the method comprising:
- using a host microprocessor to transfer data to a system memory over a peripheral bus;
- using a USB host controller to retrieve the data from the system memory;
- using an on-chip RAM in the USB host controller to store transfer descriptors sent from the host microprocessor;
- using the USB host controller to execute a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across an interface, wherein the transfer involves an amount of data specified by the single transfer descriptor without intervention by the host microprocessor;
- and
- handling both Start Split (SS) and Complete Split (CS) transactions with the single transfer descriptor.
A Universal Serial Bus (USB) host controller that handles split transactions, wherein the USB host controller comprises:
- an on-chip RAM connected to an interface, the on-chip RAM storing transfer descriptors sent from a host microprocessor;
- registers that support the RAM;
- and
- a host controller logic unit connected by an internal bus to the registers, wherein the USB host controller executes a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across the interface, the transfer involving an amount of data specified by the single transfer descriptor without any intervention by the host microprocessor;
- wherein the single transfer descriptor handles both Start Split (SS) and Complete Split (CS) transactions.
Dependencies are inferred from the claim text.