Interconnect, bus system with interconnect and bus system operating method
AssigneeSamsung Electronics Co., Ltd.
InventorsJoon-Woo Cho, Jong Ho Roh, Jae Geun Yun, Sung-Min Hong
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Abstract
Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.
Claims14
A system on chip comprising:
- masters respectively configured to access a slave, among at least first and second slaves, via an interconnect, wherein the interconnect is configured to arbitrate between multiple request signals received from the masters, receive a master address from a requesting master selected among the masters, and enable a data access operation directed to the slave by the requesting master in accordance with at least first and second bits of the master address, and
- the interconnect comprising:
- a register that stores address bit information specifying the first and second bits;
- a bit selector that selects the first and second bits in response to the address bit information;
- a logic circuit that logically combines bits including the first and second bits to generate a selection signal;
- and
- a switching circuit that in response to the selection signal converts a portion of the master address into one of a first slave address for the first slave and a second slave address for the second slave.
An interconnect connecting a requesting master with a selected slave among at least first and second slaves, the interconnect comprising:
- an interleaving block that receives a master address from the requesting master and enables a data access operation directed to the selected slave;
- and
- a register that stores address bit information specifying at least first and second bits of the master address,
- wherein the interleaving block comprises;
- a bit selector that selects at least the first and second bits in response to the address bit information;
- a logic circuit that logically combines bits including at least the first and second bits to generate a selection signal;
- and
- a switching circuit that in response to the selection signal converts a portion of the master address into one of a first slave address for the first slave and a second slave address for the second slave.
An operating method for a system on chip comprising a plurality of masters including a requesting master, at least first and second slaves, and an interconnect connecting at least the requesting master and the first and second slaves, the method comprising:
- providing a master address from the requesting master to the interconnect;
- selecting at least first and second bits of the master address within the interconnect in response to the address bit information stored in a register;
- logically combining at least the first and second bits to generate a selection signal;
- converting a portion of the master address into one of a first slave address for the first slave and a second slave address for the second slave in response to the selection signal to selective enable access to one of the first and second slaves by the requesting master.
A method of operating a system on chip, comprising:
- receiving in an interconnect respective request signals from a plurality of masters;
- by operation of the interconnect, returning a grant signal to a requesting master selected from the plurality of masters;
- providing a master address from the requesting master to the interconnect;
- selecting at least first and second bits of the master address within the interconnect in response to address bit information stored in a register;
- logically combining bits including at least the first and second bits to generate a selection signal;
- and
- converting a portion of the master address into one of a first slave address for the first slave and a second slave address for the second slave in response to the selection signal to selectively enable a data access operation directed to one of the first and second slaves by the requesting master.
Dependencies are inferred from the claim text.