Rate controlled first in first out (FIFO) queues for clock domain crossing

A method comprising:

• receiving, by a device, an indication that a read operation has been performed on one of a plurality of asynchronous first in, first out (FIFO) queues;
• incrementing, by the device, a credit counter, of a plurality of credit counters, corresponding to one of the plurality of asynchronous FIFO queues based on the indication that the read operation has been performed;
• determining, by the device, whether at least one of the plurality of credit counters includes a value greater than a threshold value;
• subtracting, by the device and based on determining that at least one of the plurality of credit counters includes the value greater than the threshold value, the threshold value from all of the plurality of credit counters;
• and
• generating, by the device and based on determining that at least one of the plurality of credit counters includes the value greater than the threshold value, a write pulse signal to control a producer clock domain to perform a write operation to each of the plurality of asynchronous FIFO queues.

A device comprising:

• a memory;
• and
• one or more processors to:
• receive data from a producer clock domain through a corresponding plurality of asynchronous first in, first out (FIFO) queues;
• receive a read clock signal indicating a read operation has been performed by a corresponding consumer clock domain that receives a portion of the data;
• reduce a frequency of the read clock signal;
• maintain a count value relating to an amount of the portion of the data read by the corresponding consumer clock domain;
• determine that the count value satisfies a threshold;
• reduce, based on determining that the count value satisfies the threshold, the count value;
• and
• issue, based on determining that the count value satisfies the threshold, a write pulse signal to the producer clock domain,
• the write pulse signal causing the producer clock domain to perform a write operation to each of the plurality of asynchronous FIFO queues.