Multi-bank queuing architecture for higher bandwidth on-chip memory buffer
AssigneeJuniper Networks, Inc.
InventorsAnurag Agrawal, Philip A. Thomas
Life of this patent
Estimating the term…
Abstract
A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.
Claims20
A method comprising:
- performing, by a network device, a write operation to move a first packet to a first bank of a memory;
- selecting, by the network device and while performing at least a portion of the write operation, an output queue to perform a read operation to remove a second packet from a second bank of the memory;
- receiving, by the network device, a bank indicator for the output queue,
- the bank indicator identifying the second bank as an odd bank or an even bank that is assigned for the read operation;
- reading, by the network device, a pointer from a pointer memory based on the bank indicator;
- retrieving, by the network device and from a data structure, an address of the second packet based on reading the pointer;
- providing, by the network device and to the memory, the address of the second packet;
- writing, by the network device and to the pointer memory, an updated pointer for the data structure;
- and
- forwarding, by the network device, the second packet.
A device comprising:
- one or more processors to:
- perform a write operation to move a first packet to a first bank of a memory;
- select an output queue to perform a read operation to remove a second packet from a second bank of the memory;
- receive a bank indicator for the output queue,
- the bank indicator identifying the second bank as an odd bank or an even bank that is assigned for the read operation;
- identify a pointer memory based on the bank indicator;
- retrieve, from a data structure, an address of the second packet;
- provide the address of the second packet to the memory;
- and
- write an updated pointer for the data structure to the pointer memory.
A non-transitory computer-readable medium storing instructions, the instructions comprising:
- one or more instructions that, when executed by a device, cause the device to:
- perform a write operation to move a first packet to a first bank of a memory;
- select an output queue to perform a read operation to remove a second packet from a second bank of the memory;
- receive a bank indicator for the output queue,
- the bank indicator identifying the second bank as an odd bank or an even bank that is assigned for the read operation;
- determine information identifying a pointer memory based on the bank indicator;
- retrieve, from a data structure, an address of the second packet;
- provide the address of the second packet to the memory;
- write an updated pointer for the data structure to the pointer memory;
- and
- forward the second packet.
Dependencies are inferred from the claim text.