Scalable architecture for rank order filtering
AssigneeXilinx, Inc.
InventorsPeter Szanto, Gabor Szedo, Bela Feher, Wilson C. Chung
Life of this patent
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Abstract
A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.
Claims6
A rank order filter, comprising:
- the rank order filter being associated with a virtual filter window, the virtual filter window being a number NZ+1 concatenated real filter windows;
- the number NZ+1 being a height of the virtual filter window minus a height of the real filter windows, wherein each of the real filter windows are of a same dimension;
- a filter core including a stage of data registers, a stage of comparison blocks configured for registering compare results, and a stage of shift registers;
- the virtual filter window configured for input of an integer multiple of NI samples to the filter core;
- the filter core configured for input of the NI samples on a clock cycle of a filter core clock;
- wherein the filter core inputs the integer multiple of the NI samples for a number of clock cycles of the filter core clock, the number of the clock cycles being equivalent to the integer multiple;
- wherein the virtual filter window spans padding samples, the padding samples capable of being part of the NI samples;
- wherein the NI samples are capable of including both real samples and the padding samples, the real samples being associated with actual pixel information;
- and
- the filter core configured to make available all of the compare results for the stage of shift registers for generating NZ+1 outputs on each clock cycle of the filter core clock.
Dependencies are inferred from the claim text.