Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
Estimating the term…
Abstract
A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
Claims21
A device, comprising:
- a plurality of logic modules including a first logic module and a second logic module, the first logic module configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit, the second logic module configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit;
- logic circuitry configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the quaternary addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.
A logic circuitry including a quaternary adder, the logic circuitry comprising:
- a first logic circuitry configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit;
- a second logic circuitry configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit in the same clock cycle the first carry bit is output;
- and
- a third logic circuitry configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.
A device, comprising:
- first logic circuitry means configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit;
- second logic circuitry means configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit in the same clock cycle the first carry bit is output;
- third logic circuitry means configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.
Dependencies are inferred from the claim text.