IR(voltage) drop analysis in integrated circuit timing

A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed:

• determine one or more first timing parameters for a cell, including effects of parasitic impedances on a power supply grid within the cell;
• determine one or more second timing parameters for the cell, excluding effects of parasitic impedances on the power supply grid;
• compare the one or more first timing parameters to the one or more second timing parameters;
• perform timing analysis on a circuit including the cell using third timing parameters that include a margin for a voltage drop in the cell;
• and
• determine whether or not the cell requires refinement responsive to a result of the compare, wherein the cell requires refinement if a difference between at least one of the first timing parameters and a corresponding one of the second timing parameters exceeds the margin in a corresponding one of the third timing parameters that is budgeted for the voltage drop in the cell.

A computer system comprising:

• at least one processor configured to execute instructions;
• and
• a non-transitory computer accessible storage medium coupled to the at least one processor, the computer accessible medium storing:
• a characterization tool;
• an extraction tool;
• and
• a program which, when executed by the at least one processor:
• invokes the characterization tool to characterize a plurality of cells with an ideal power supply;
• invokes the extraction tool to extract power parasitic impedances from the plurality of cells;
• invokes the characterization tool to characterize a plurality of cells including the power parasitic impedances;
• and
• identifies which of the plurality of cells are to be refined responsive to differences in one or more timing parameters generated by the characterization tool using the ideal power supply and with the power parasitic impedances, wherein which of the plurality of cells are to be refined are those for which the differences in the one or more timing parameters exceed a predetermined margin used for timing impacts of a voltage drop in the cell, wherein the predetermined margin is applied to second timing parameters used for performing timing analysis on a circuit that includes the cell.

A method comprising:

• simulating, on a computer, a first model of a circuit, wherein the first model includes parasitic impedances on signal connections and an ideal power supply;
• determining, on the computer, a first set of delays through the circuit responsive to simulating the first model;
• extracting, on the computer, power parasitic impedances;
• simulating, on the computer, a second model of the circuit, wherein the second model includes the power parasitic impedances and connections to ideal power supplies at points on a power grid corresponding to the circuit at which the circuit is coupled to a global power supply grid of an integrated circuit;
• determining, on the computer, a second set of delays through the circuit responsive to simulating the second model;
• comparing, on the computer, the first set of delays and the second set of delays;
• and
• identifying the circuit for additional design work responsive to the comparing wherein the identifying is performed responsive to a difference between a first delay in the first set and the second set exceeding a threshold, and wherein the threshold is based on a margin added to the delay for voltage drop on the power supply grid, wherein the margin is applied to a third set of delays used for timing analysis of another circuit that includes the circuit.

A non-transitory computer accessible storage medium storing:

• a first cell model corresponding to a first cell, the first cell model excluding power parasitic impedances;
• a second cell model corresponding to the first cell, the second cell model including power parasitic impedances extracted from a layout of the first cell;
• a plurality of instructions which, when executed:
• determine a first delay through the first cell responsive to the first cell model;
• determine a second delay through the first cell responsive to the second cell model;
• determine that the second delay exceeds the first delay by an amount that is greater than a second amount budgeted for an effect of the power parasitic impedances, wherein the second amount is applied to a third delay used for timing analysis of a circuit that includes the first cell;
• and
• identify the first cell for modification of a power grid associated with the first cell responsive to determining that the second delay exceeds the first delay by the amount that is greater than the second amount.