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US 8,712,718 B1Granted
Predicting performance of an integrated circuit
AssigneeXilinx, Inc.
InventorsRafael C. Camarota, David L. Ferguson, Geoffrey Richmond
Life of this patent
Estimating the term…
Abstract
A method of characterizing a die can include correlating, using a processor, a static voltage profile of a die under test in wafer form with a plurality of test static voltage profiles. The plurality of test static voltage profiles can be associated with dynamic performance profiles. The method further can include predicting dynamic performance of the die under test according to the dynamic performance profile associated with a test static voltage profile that is correlated with the static voltage profile.
Claims14
A method comprising:
- storing a test static voltage profile for each of a plurality of dies tested in wafer form, wherein each test static voltage profile specifies a static voltage measured at a node of a circuit within the die;
- storing a dynamic performance profile for each of the plurality of dies determined after packaging of the die, wherein each test static voltage profile is associated with the dynamic performance profile for the same die of the plurality of dies;
- determining a static voltage profile of a die under test in wafer form by measuring a static voltage of a node of a circuit of the die under test;
- matching, using a processor, the static voltage profile of the die under test in wafer form with a test static voltage profile of the plurality of test static voltage profiles;
- assigning the dynamic performance profile associated with the matched test static voltage profile to the die under test;
- and
- classifying the die under test into one of a plurality of different performance groups according to the assigned dynamic performance profile.
4 more elements
A system, comprising:
- a memory storing program code;
- and
- a processor coupled to the memory, wherein responsive to executing the program code, the processor is configured to perform executable operations comprising:
- storing a test static voltage profile for each of a plurality of dies tested in wafer form, wherein each test static voltage profile specifies a static voltage measured at a node of a circuit within the die;
- storing a dynamic performance profile for each of the plurality of dies determined after packaging of the die, wherein each test static voltage profile is associated with the dynamic performance profile for the same die of the plurality of dies;
- determining a static voltage profile of a die under test in wafer form by measuring a static voltage of a node of a circuit of the die under test;
- matching the static voltage profile of the die under test in wafer form with a test static voltage profile of the plurality of test static voltage profiles;
- assigning the dynamic performance profile associated with the matched test static voltage profile to the die under test;
- and
- classifying the die under test into one of a plurality of different performance groups according to the assigned dynamic performance profile.
7 more elements
An apparatus, comprising:
- a die,
- wherein the die is in wafer form and comprises:
- an input port configured to receive configuration data for the die;
- a circuit placed in a known operating state responsive to loading the configuration data;
- an analog-to-digital (A/D) converter coupled to a node of the circuit responsive to loading the configuration data, wherein the A/D converter is configured to sample a static voltage of the node;
- an output port configured to output the sampled static voltage;
- and
- a non-volatile memory coupled to the input port;
- wherein the non-volatile memory stores a classification of the die written to the non-volatile memory during wafer testing, wherein the classification indicates a performance group of dies to which the die is assigned.
6 more elements
Dependencies are inferred from the claim text.