Image processor
AssigneeMegaChips Corporation
InventorsToshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
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AssigneeMegaChips Corporation
InventorsToshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
Estimating the term…
An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame. The controller includes a first processing unit that obtains a generated amount of code used for a first predetermined number of immediately preceding macroblocks, a second processing unit that obtains an allowable amount of code available for a third predetermined number of immediately subsequent macroblocks including a currently target macroblock, based on a target amount of code for not more than a second predetermined number of macroblocks less than a total number of macroblocks included in one frame, and the generated amount of code obtained by the first processing unit, a third processing unit that obtains an expected amount of code expected to be used for the third predetermined number of macroblocks, and a fourth processing unit that sets a quantization parameter of a currently target macroblock, based on the allowable amount of code obtained by the second processing unit and the expected amount of code obtained by the third processing unit.
An image processor comprising:
Dependencies are inferred from the claim text.