Amplitude-shift-keying (ASK) envelope detector and demodulation circuits

An amplitude envelope detector comprising:

• an input receiving an amplitude-modulated or an Amplitude-Shift-Keying (ASK) encoded input signal wherein a carrier wave has modulated peak voltages;
• first sample switch means for conducting current in response to a first sampling clock;
• first rectifier means for permitting current flow in a forward direction and for blocking current flow in a reverse direction that is opposite to the forward direction;
• wherein the first sample switch means and the first rectifier means are in series between the input and a first channel node;
• first sampling capacitor means for storing charge on the first channel node;
• first reset switch means for discharging the first sampling capacitor means in response to a first reset clock;
• first hold switch means for conducting a first charge from the first channel node to a first output node in response to a first hold clock;
• second sample switch means for conducting current in response to a second sampling clock;
• second rectifier means for permitting current flow in a forward direction and for blocking current flow in a reverse direction that is opposite to the forward direction;
• wherein the second sample switch means and the second rectifier means are in series between the input and a second channel node;
• second sampling capacitor means for storing charge on the second channel node;
• second reset switch means for discharging the second sampling capacitor means in response to a second reset clock;
• second hold switch means for conducting a second charge from the second channel node in response to a second hold clock;
• combination means for combining the first charge and the second charge to generate an envelope signal, wherein the envelope signal varies with the modulated peak voltages of the input.

A multi-channel envelope detect circuit comprising:

• a modulated input receiving an amplitude-modulated or an Amplitude-Shift-Keying (ASK) encoded input signal wherein a carrier wave has modulated peak voltages;
• a first sample switch clocked by a first sampling clock to conduct to a first internal node during a first cycle of the carrier wave;
• a combined rectifier connected between the modulated input and the first sample switch to permit current flow in a forward direction to a rectifier node and to block current flow in a reverse direction;
• a first sampling capacitor on the first internal node for storing a first sampled charge that is a function of a modulated peak voltage of the modulated input during the first cycle;
• a first reset switch on the first internal node for discharging the first sampled charge on the first sampling capacitor in response to a first reset clock;
• a first hold switch, coupled between the first internal node and a summing node, and clocked by a first hold clock to conduct after the first cycle is completed;
• a second sample switch clocked by a second sampling clock to conduct from the rectifier node to a second internal node during a second cycle of the carrier wave;
• a second sampling capacitor on the second internal node for storing a second sampled charge that is a function of a the modulated peak voltages of the modulated input during the second cycle;
• a second reset switch on the second internal node for discharging the second sampled charge on the second sampling capacitor in response to a second reset clock;
• a second hold switch, coupled between the second internal node and the summing node, and clocked by a second hold clock to conduct after the second cycle is completed;
• and
• a summing capacitor on the summing node, the summing capacitor generating an output voltage that tracks the modulated peak voltages of the modulated input.