Partial response decision feedback equalizer with distributed control

A multi-phase partial response equalizer comprising:

• receiver circuitry to receive a data symbol and generate first and second sets of samples in response to respective first and second clock signals having different phases;
• a first stage of storage elements to receive the first and second sets of samples in a common timing domain, the first stage to store the first set of samples and a conditional selection from the second set of samples, the conditional selection based on the first set of samples;
• and
• a second stage of storage elements to store a selected first output sample from the conditional selection, the selected first output sample based on the value of a previous output sample from the second stage, and a selected second output sample from the stored first set of samples based on the value of the previous output sample.

A method of equalizing comprising:

• receiving a data symbol and generating first and second sets of conditional samples in response to first and second clock signals having different phases, the sets of conditional samples corresponding to respective bit intervals;
• producing conditional selections from the second set of conditional samples using a first selection circuit;
• storing the samples from the first set and the conditional selections from the second set in a first storage stage;
• and
• selecting an output sample with a second selection circuit from each of (1) the samples from the first set and (2) the conditional selections dependent upon a previous symbol.

A multi-phase partial response receiver to receive an input signal, comprising:

• a plurality of samplers, at least two for each phase of the input signal, the samplers for each phase applying respective thresholds to the input signal to produce conditional samples;
• alignment circuitry to align the conditional samples to a common clock phase;
• a first selection stage including at least two first-stage multiplexers,
• each first-stage multiplexer to receive each of the conditional samples for a second one of the phases of the input signal at the common clock phase,
• the first-stage multiplexers receiving as selection control signals respective ones of the conditional samples for a first one of the phases, each first-stage multiplexer selecting between the conditional samples for the second one of the phases and producing an output;
• a first delay stage to receive and delay
• the conditional samples for the first one of the phases, and
• the first-stage multiplexer outputs;
• and
• a second selection stage including
• a first second-stage multiplexer that selects between the delayed conditional samples for the first one of the phases, and
• a second second-stage multiplexer that selects between the delayed outputs of the first stage multiplexers.

A multi-phase partial response equalizer comprising:

• receiver circuitry to receive a data symbol over first and second bit intervals and to generate a first set of conditional samples in response to the first bit interval, and a second set of conditional samples in response to the second bit interval;
• alignment circuitry to align the first and second sets to a substantially common timing phase;
• conditional selection circuitry to generate two conditional selections for the second set based on the conditional samples in the first set;
• a storage stage to store the two conditional selections and the first set of conditional samples;
• and
• sample selection circuitry to generate a first phase data output based on the first set of conditional samples and a second phase data output based on the two conditional selections, each data output being selected according to a prior second phase data output.

A multi-phase partial response equalizer comprising:

• a sampling stage to generate plural conditional samples for each phase of an input signal;
• a first selection stage to generate a conditional selection from amongst at least two conditional samples for one of the phases of the input signal;
• a first storage stage to store the conditional selection as well as at least two of the plural conditional samples;
• and
• a second selection stage to select a data output for each phase of the input signal, the second selection stage performing selection for each phase of the input signal based upon a common feedback value.