Signal processing apparatus, display apparatus having the same, and signal processing method

A signal processing apparatus comprising:

• an input configured to receive a first number of transmission stream signals in parallel;
• and
• a multiplexer configured to group the first number of transmission stream signals according to kinds thereof, and output a second number of transmission stream signals, the second number being less than the first number,
• wherein the transmission stream signals comprise a clock signal, a synchronous signal, a valid signal, and eight data signals, and
• wherein the multiplexer groups the synchronous signal and the valid signal into one first group signal, groups the eight data signals into second to fifth group signals, and outputs the clock signal, the first group signal, and the second to fifth group signals.

A signal processing method comprising:

• receiving a first number of transmission stream signals in parallel;
• generating a second number of transmission stream signals by grouping the first number of transmission stream signals according to kinds thereof;
• and
• outputting the generated second number of transmission stream signals,
• wherein the second number is less than the first number,
• wherein the transmission stream signals comprise a clock signal, a synchronous signal, a valid signal, and eight data signals, and
• wherein the generating the second number of transmission stream signals comprises:
• grouping the synchronous signal and the valid signal into one first group signal;
• grouping the eight data signals into second to fifth group signals;
• and
• providing the clock signal, the first group signal, and the second to fifth group signals as the second number of transmission stream signals.

A display apparatus comprising:

• a first signal processor configured to group a plurality of transmission stream signals according to kinds thereof, and output the grouped signals on an internal high speed data interface of the display apparatus according to an internal clock of the display apparatus;
• a second signal processor configured to receive the grouped signals from the internal high speed data interface of the display apparatus, restore the grouped signals into the plurality of transmission stream signals, and output the restored transmission stream signals,
• wherein a number of the transmission stream signals is greater than a number of the grouped signals,
• wherein the transmission stream signals comprise a clock signal, a synchronous signal, a valid signal, and eight data signals, and
• wherein the first signal processor groups one of the synchronous signal and the valid signal into a first group signal and the eight data signals into second to fifth group signals, and outputs the clock signal, the first group signal, and the second to fifth group signals to the internal high speed interface according to the internal clock.