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US 8,711,653 B2Granted
Changing a system clock rate synchronously
AssigneeHewlett-Packard Development Company, L.P.
InventorsVijaykumar Nayak, Prajna Raghavendra Poorna
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Abstract
A system includes a shared memory and a plurality of processor cores communicatively coupled to the shared memory. The system includes a processor core memory and a clock subsystem for providing a clock signal to the shared memory and the plurality of processor cores. Each of the plurality of processor cores executes instructions stored in the processor core memory for synchronously changing the clock rate provided by the clock subsystem to the plurality of processor cores.
Claims15
A system comprising:
- a shared memory;
- a plurality of processor cores communicatively coupled to the shared memory;
- a processor core memory;
- and
- a clock subsystem for providing a clock signal to the shared memory and the plurality of processor cores,
- wherein each of the plurality of processor cores executes instructions stored in the processor core memory for synchronously changing the clock rate provided by the clock subsystem to the plurality of processor cores.
3 more elements
A system comprising:
- a Dynamic Random Access Memory (DRAM);
- a plurality of processor cores communicatively coupled to the DRAM;
- a processor core memory;
- a plurality of Direct Memory Access (DMA) clients communicatively coupled to the DRAM, each of the DMA clients subscribed to one of the processor cores;
- and
- a clock subsystem for providing a clock signal to the DRAM, the plurality of processor cores, and the plurality of DMA clients,
- wherein each of the processor cores executes instructions stored in the processor core memory to synchronously change the clock rate provided by the clock subsystem.
4 more elements
A method comprising:
- notifying, via a primary processor core, registered clients in a system including a plurality of processor cores to stop accessing a shared Dynamic Random Access Memory (DRAM);
- receiving, at the primary processor core, confirmation from the registered clients that the registered clients have stopped accessing the shared DRAM;
- entering a self refresh mode for the shared DRAM;
- changing a clock rate of a clock signal provided to each of the plurality of processor cores and each registered client;
- exiting a self refresh mode for the shared DRAM;
- and
- notifying, via the primary processor core, the registered clients of completion of the clock rate change.
4 more elements
Dependencies are inferred from the claim text.