DRAM refresh method and system
AssigneeInphi Corporation
InventorDavid Wang
Life of this patent
Estimating the term…
Abstract
A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times.
Claims32
A method of refreshing DRAM in a memory system organized into rows of memory cells, each of said cells having an associated data retention time, said memory system arranged to refresh predefined blocks of said memory cells simultaneously, comprising:
- for each predefined block of memory cells that are to be refreshed simultaneously, determining the minimum data retention time for the memory cells in the block;
- and
- creating an asymmetric refresh sequence which specifies the order in which said blocks of memory cells are to be refreshed, such that said blocks of memory cells having the shortest minimum data retention times are refreshed more often than the blocks of memory cells having longer minimum data retention times.
A memory system comprising DRAM organized into rows of memory cells, each of said cells having an associated data retention time, said memory system arranged to refresh predefined blocks of said memory cells simultaneously, comprising:
- retention time characterization circuitry to determine the minimum data retention times for the memory cells in each block of memory cells that are to be refreshed simultaneously;
- processing circuitry to receive the minimum data retention times from said retention time characterization circuitry and to create an asymmetric refresh sequence based on said data which specifies the order in which said blocks of memory cells are to be refreshed, such that the blocks of memory cells having the shortest minimum data retention times are refreshed more often than the blocks of memory cells having longer minimum data retention times;
- and
- a storage device which stores said asymmetric refresh sequence.
Dependencies are inferred from the claim text.