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US 8,711,643 B2Granted
Memory interface circuit, memory interface method, and electronic device
AssigneeFujitsu Semiconductor Limited
InventorYoshiharu Kato
Life of this patent
Estimating the term…
Abstract
A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.
Claims14
A memory interface circuit comprising:
- a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command;
- a clamp circuit that clamps the data strobe signal to a first logic level after the data read command is issued;
- and
- a detection circuit that detects a logic level of the data strobe signal, which is driven by a memory, in accordance with the data read command, wherein
- the gating circuit includes a first input terminal that receives the data read command and a second input terminal that receives the data strobe signal, and
- the clamp circuit is coupled to the second input terminal of the gating circuit to clamp the data strobe signal to the first logic level.
3 more elements
A memory interface method comprising:
- clamping a data strobe signal to a first logic level after a data read command is issued;
- and
- starting detection of a logic level of the data strobe signal, which is driven by a memory, in accordance with the data read command, wherein
- the data read command is input to a first input terminal of a gating circuit, the data strobe signal is input to a second input terminal of the gating circuit, and the data strobe signal is clamped to the first logic level by a clamp circuit coupled to the second input terminal of the gating circuit.
1 more element
An electronic device comprising:
- a controller;
- a memory;
- and
- a memory interface circuit arranged between the controller and the memory, wherein the memory interface circuit accesses the memory in accordance with a command from the controller and includes
- a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command from the controller,
- a clamp circuit that clamps the data strobe signal to a first logic level after the data read command is issued, and
- a detection circuit that detects a logic level of the data strobe signal, which is driven by the memory, in accordance, with the data read command, wherein
- the gating circuit includes a first input terminal that receives the data read command and a second input terminal that receives the data strobe signal, and
- the clamp circuit is coupled to the second input terminal of the gating circuit to clamp the data strobe signal to the first logic level.
6 more elements
Dependencies are inferred from the claim text.