Data paths using a first signal to capture data and a second signal to output data and methods for providing data
AssigneeMicron Technology, Inc.
InventorLee Eric
Life of this patent
Estimating the term…
Abstract
Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
Claims21
A data path, comprising:
- a delay path configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that is approximately the same as a data propagation delay of the data path;
- and
- a clocked data register coupled to the delay path and configured to capture data responsive at least in part to the delayed clock signal and further configured to provide the data responsive at least in part to the clock signal.
A data path, comprising:
- a clocked data register configured to capture data responsive to a first clock signal and to provide the data responsive to a second clock signal;
- and
- a delay path coupled to the clocked data register and configured to receive the second clock signal and provide the first clock signal to the clocked data register, the first clock signal having a delay relative to the second clock signal, and wherein the first clock signal is provided by the delay path to clock the data into the clocked data register.
A memory, comprising:
- a memory array configured to store data;
- a data cache register coupled to the memory array and configured to receive the data from the memory array;
- a delay path coupled to the data cache register and configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that is approximately equal to a propagation delay;
- and
- a clocked data register coupled to the delay path and configured to capture the data responsive at least in part to the delayed clock signal and further configured to provide the data responsive at least in part to the clock signal.
A method for providing data from memory, comprising:
- providing the data from a data cache register to a FIFO register responsive to a first clock signal;
- loading the data into the FIFO register asynchronously responsive to a second clock signal having a delay relative to the first clock signal;
- and
- providing the data from the FIFO register synchronously responsive to the first clock signal.
A method for providing data from memory, comprising:
- loading a FIFO register with the data responsive at least in part to a first clock signal, the data provided from a data cache register to the FIFO register, the first clock signal having a delay relative to a second clock signal approximately equal to a data propagation delay from the data cache register to the FIFO register;
- and
- providing the data from the FIFO register and providing the data from the data cache register responsive at least in part to the second clock signal.
Dependencies are inferred from the claim text.