Semiconductor device and data processing system
AssigneeHitachi, Ltd.
InventorsSeiji Miura, Satoru Hanzawa
Life of this patent
Estimating the term…
Abstract
In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.
Claims20
A semiconductor device comprising:
- a plurality of memory cells each having rewritable resistive storage elements disposed at intersections between a plurality of word lines and a plurality of bit lines intersecting the word lines;
- and
- a write driver for writing data to each of the memory cells respectively,
- wherein the write driver, when writing an M bit data, performs erase operation and program operation in units of n bit (M>n) data.
The semiconductor device according to claim
- wherein the resistance is set low only for the resistive storage elements in the memory cell to which the write data “1” is written among the memory cells for n bits as the rewrite target in the program operation.
A data processing system comprising a data processing device, a control device and a memory device,
- wherein the control device is a device for controlling the memory device in accordance with a write demand from the data processing device,
- wherein the memory device includes a memory bank and a buffer,
- wherein the write demand contains a write instruction, a first write address, a write data size, and a write data, and
- wherein the control device transfers the write data only for the write data size to the buffer in accordance with the write instruction from the data processing device and with the first write address being as a start address, and then writes the data to the memory bank.
A semiconductor device comprising:
- a first memory bank and a second memory bank each having a plurality of storage elements for storing data, the first memory bank having a first buffer and a second buffer, and the second memory bank having a third buffer and a fourth buffer,
- wherein the control circuit performs read operation from the first memory bank to the second buffer during write operation to the first buffer, or
- reads the second data held in the second buffer during writing of the first data held in the first buffer to the first memory bank.
Dependencies are inferred from the claim text.