US 8,711,632 B2Granted

Semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorAkira Katayama

Life of this patent

Estimating the term…

Loading patent…

Abstract

The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.

Claims19

Dependent claims

A semiconductor memory device comprising:

a first cell array including first memory cells arranged in a matrix, the first memory cell having a first variable resistance element and a first select transistor;
a second array including second memory cells arranged in a matrix, the second memory cell having a second variable resistance element and a second select transistor;
a first reference-current setting circuit configured to output a first reference current based on a current passing through a first reference cell selected from the first cell array;
a second reference-current setting circuit configured to output a second reference current based on a current passing through a second reference cell selected from the second cell array;
a sense amplifier circuit configured to compare a current passing through a selected bit line to the second reference current during a first read operation of the first memory cell selected from the first cell array, the sense amplifier circuit being configured to output a first reading signal according to a comparison result during the first read operation, the sense amplifier circuit being configured to compare a current passing through a selected bit line to the first reference current during a second read operation of the second memory cell selected from the second cell array, the sense amplifier circuit being configured to output a second reading signal according to a comparison result during the second read operation;
and
a control circuit that controls the first and second reference-current setting circuits,
wherein the control circuit selects, as the first reference cell, the first memory cell being capable of passing a maximum reading current supplied by turning on the first select transistor,
the control circuit selects, as the second reference cell, the second memory cell being capable of passing a maximum reading current supplied by turning on the second select transistor,
the first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell, and
the second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.

8 more elements

A semiconductor memory device comprising:

a first cell array including first memory cells arranged in a matrix, the first memory cell having a first variable resistance element and a first select transistor;
a second array including second memory cells arranged in a matrix, the second memory cell having a second variable resistance element and a second select transistor;
a first reference-current setting circuit configured to output a first reference current based on a current passing through a first reference cell selected from the first cell array;
a second reference-current setting circuit configured to output a second reference current based on a current passing through a second reference cell selected from the second cell array;
a sense amplifier circuit configured to compare a current passing through a selected bit line to the second reference current during a first read operation of the first memory cell selected from the first cell array, the sense amplifier circuit being configured to output a first reading signal according to a comparison result during the first read operation, the sense amplifier circuit being configured to compare a current passing through a selected bit line to the first reference current during a second read operation of the second memory cell selected from the second cell array, the sense amplifier circuit being configured to output a second reading signal according to a comparison result during the second read operation;
and
a control circuit that controls the first and second reference-current setting circuits,
wherein the control circuit selects, as the first reference cell, the first memory cell being capable of passing a minimum reading current supplied by turning on the first select transistor,
the control circuit selects, as the second reference cell, the second memory cell being capable of passing a minimum reading current supplied by turning on the second select transistor,
the first reference-current setting circuit sets, as the first reference current, a current obtained by subtracting a first adjusting current from the reading current of the first reference cell, and
the second reference-current setting circuit sets, as the second reference current, a current obtained by subtracting a second adjusting current from the reading current of the second reference cell.

8 more elements

A semiconductor memory device comprising:

a first cell array including first memory cells arranged in a matrix, the first memory cell having a first variable resistance element and a first select transistor;
a second array including second memory cells arranged in a matrix, the second memory cell having a second variable resistance element and a second select transistor;
a first reference-current setting circuit configured to output a first reference current;
a second reference-current setting circuit configured to output a second reference current;
a sense amplifier circuit configured to compare a current passing through a selected bit line to the second reference current during a first read operation of the first memory cell selected from the first cell array, the sense amplifier circuit being configured to output a first reading signal according to a comparison result during the first read operation;
and
a control circuit that controls the first and second reference-current setting circuits,
wherein the first reference-current setting circuit sets, as the first reference current, a current between a first reading current of the first memory cell having a maximum reading current and a second reading current of the first memory cell having a minimum reading current, the maximum reading current being a current supplied by turning on the first select transistor in a state in which resistance values of all of the first memory cells are all increased, and the minimum reading current being a current supplied by turning on the first select transistor in a state in which resistance values of all of the first memory cells are all reduced, and
the second reference-current setting circuit sets, as the second reference current, a current between a third reading current of the second memory cell having a maximum reading current and a fourth reading current of the second memory cell having a minimum reading current, the maximum reading current being a current supplied by turning on the second select transistor in a state in which resistance values of all of the second memory cells are all increased, and the minimum reading current being a current supplied by turning on the second select transistor in a state in which resistance values of all of the second memory cells are all reduced.

6 more elements

Dependencies are inferred from the claim text.