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US 8,711,629 B2Granted
Nonvolatile semiconductor memory device
AssigneePanasonic Corporation
InventorsMasayoshi Nakayama, Takashi Ono, Reiji Mochida
Life of this patent
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Abstract
Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit.
Claims10
A nonvolatile semiconductor memory device, comprising:
- a memory array having a plurality of nonvolatile memory cells arranged using a virtual ground, a word line for control of a gate and first and second bit lines being connected to each of the nonvolatile memory cells;
- a first selective transistor group for selecting the first bit line;
- a first selective transistor drive circuit configured to drive gates of the first selective transistor group;
- a second selective transistor group for selecting the second bit line;
- a second selective transistor drive circuit configured to drive gates of the second selective transistor group;
- a first voltage switch configured to select a voltage to be supplied to the first selective transistor drive circuit depending on an operation of the memory array;
- and
- a second voltage switch configured to select a voltage to be supplied to the second selective transistor drive circuit depending on the operation of the memory array, wherein
- a transistor constituting the first selective transistor drive circuit is different in structure from a transistor constituting the second selective transistor drive circuit.
6 more elements
Dependencies are inferred from the claim text.