Back to results
US 8,711,619 B2Granted
Categorizing bit errors of solid-state, non-volatile memory
AssigneeSeagate Technology LLC
InventorsAra Patapoutian, Arvind Sridharan
Life of this patent
Estimating the term…
Abstract
Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category.
Claims19
A method, comprising:
- assigning bit errors affecting cells of a solid-state, non-volatile memory to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells, wherein the first and second categories are based on conditional probabilities of actual values read from the cells in view of expected values of the cells;
- adjusting a reference voltage used to access the respective cells to manage the respective bit errors of the first category;
- and
- taking additional corrective measures to manage the respective bit errors of the second category.
1 more element
An apparatus, comprising:
- a controller capable of being coupled to a solid-state, non-volatile memory, the controller configured to:
- assign bit errors affecting cells of the solid-state, non-volatile memory to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells, wherein the first and second categories are based on conditional probabilities of actual values read from the cells in view of expected values of the cells;
- adjust a reference voltage used to access the respective cells to manage the respective bit errors of the first category;
- and
- take additional corrective measures to manage the respective bit errors of the second category.
2 more elements
An apparatus comprising:
- a controller capable of being coupled to a solid-state, non-volatile memory, the controller configured to:
- determining a voltage difference between an expected voltage level and an actual voltage level associated with a bit error affecting at least one cell of the solid-state, non-volatile memory;
- in response to the voltage difference satisfying a threshold based on conditional probabilities of actual values read from the cells in view of expected values of the cells, adjust a parameter used to access the cell based on the voltage difference;
- and
- take additional corrective measures to manage the bit error in response to the voltage difference not satisfying the threshold.
2 more elements
Dependencies are inferred from the claim text.