US 8,711,614 B1 · Memory elements with increased write margin and soft error upset immunity

Abstract

Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

Claims19

Dependent claims

A memory element comprising:

first and second pairs of transistors that are interconnected to form a bistable element having two nodes, each node being coupled between an n-channel transistor and a p-channel transistor in a respective one of the first and second pairs of transistors;
only one control transistor coupled in series with the first pair of transistors between a pair of power supply lines, wherein the control transistor is configured to control the first pair of transistors;
and
a third transistor pair that is interconnected with the first and second transistor pairs to form the bistable element, wherein the bistable element has a third node, the third node being coupled between an n-channel transistor and a p-channel transistor in the third transistor pair.

1 more element

A memory element comprising:

a first pair of power supply lines on which a first set of voltage levels is applied;
a second pair of power supply lines on which a second set of voltage levels is applied, wherein the first set of voltage levels is different than the second set of voltage levels;
first and second pairs of transistors that are interconnected to form a bistable element having two nodes, each node being coupled between an n-channel transistor and a p-channel transistor in a respective one of the first and second pairs of transistors, wherein each of the first and second pairs of transistors has an input and an output, wherein the input of the first pair of transistors is coupled to the output of the second pair of transistors, and wherein the output of the first pair of transistors is coupled to the input of the second pair of transistors;
and
a control transistor, wherein the control transistor is associated with the first pair of transistors, wherein the first pair of transistors and the control transistor are coupled in series between the first pair of power supply lines, and wherein the second pair of transistors is coupled between the second pair of power supply lines.

2 more elements

Dependencies are inferred from the claim text.

Memory elements with increased write margin and soft error upset immunity

Life of this patent

Memory elements with increased write margin and soft error upset immunity

Life of this patent

Abstract

Claims19