US 8,711,598 B1Granted

Memory cell and memory cell array using the same

AssigneeUnited Microelectronics Corp.

InventorsHsin-Wen Chen, Chi-Chang Shuai, Shih-Chin Lin

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Abstract

A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Claims16

Dependent claims

A memory cell, comprising:

a first P-type transistor configured to have a first source/drain thereof electrically coupled to a first voltage;
a second P-type transistor configured to have a first source/drain thereof electrically coupled to the first voltage;
a first N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the first P-type transistor, a second source/drain thereof electrically coupled to a second voltage, and a gate thereof electrically coupled to the gate of the first P-type transistor;
a second N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to the gate of the second P-type transistor;
a third N-type transistor configured to have a first source/drain thereof electrically coupled to a write word line, a second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to a first write bit line;
and
a fourth N-type transistor configured to have a first source/drain thereof electrically coupled to the write word line, a second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and a gate thereof electrically coupled to a second write bit line.

4 more elements

A memory cell array, comprising:

a plurality of write word lines;
a plurality of first write bit lines;
a plurality of second write bit lines;
and
a plurality of memory cells arranged in a matrix form, each one of the memory cells being electrically coupled to one of the write word lines, one of the first write bit lines and one of the second write bit lines, each one of the memory cells comprising:
a first P-type transistor configured to have a first source/drain thereof electrically coupled to a first voltage;
a second P-type transistor configured to have a first source/drain thereof electrically coupled to the first voltage;
a first N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the first P-type transistor, a second source/drain thereof electrically coupled to a second voltage, and a gate thereof electrically coupled to a gate of the first P-type transistor;
a second N-type transistor configured to have a first source/drain thereof electrically coupled to the second source/drain of the second P-type transistor, a second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to a gate of the second P-type transistor;
a third N-type transistor configured to have a first source/drain thereof electrically coupled to one of the write word lines, a second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and a gate thereof electrically coupled to one of the first write bit lines;
and
a fourth N-type transistor configured to have a first source/drain thereof electrically coupled to one of the write word lines, a second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and a gate thereof electrically coupled to one of the second write bit lines.

9 more elements

Dependencies are inferred from the claim text.